滤波.txt

通过使用CPLD来控制AD转换,实现实时采集数据

ENTITY fir0 IS
PORT
(clk:in Std_Logic;
x:in Std_Logic_Vector(7 DOWNTO 0);
yut Std_Logic_Vector(7 DOWNTO 0)
);
END;

ARCHITECTURE fir0_a OF fir0 IS
type del_7_8 is array(7 downto 1) of Std_Logic_Vector(7 downto 0);
--定义数组
signal qxd: del_7_8:=(x"00",x"00",x"00",x"00",x"00",x"00",x"00";
signal wy: Std_Logic_Vector(10 DOWNTO 0);

begin 
    process (clk)
    begin
        if rising_edge(clk) then
            for i in 2 to 7 loop
                qxd(i)<=qxd(i-1);
            end loop;
            qxd(1)<=x;
        end if;
    end process;
    
    precess (x,qxd)
    variable vy: Std_Logic_Vector(10 DOWNTO 0);
    begin
        vy:= x(7) & x(7) & x(7) & x;
        for i in 1 to 7 loop
                vy:= vy + (qxd(i)(7) & qxd(i)(7) & qxd(i)(7) & qxd(i));
  -- 扩展符号位，避免加法器溢出
        end loop;
        wy<=vy;
    end process;
     y<=wy(10 downto 3);
   --舍弃后三位 
    end fir0_a;