📄 fx2_to_extsyncfifo.lst
字号:
503 1 }
504
505 void ISR_Sof(void) interrupt 0
506 {
507 1 EZUSB_IRQ_CLEAR();
508 1 USBIRQ = bmSOF; // Clear SOF IRQ
509 1 }
510
511 void ISR_Ures(void) interrupt 0
512 {
513 1 // whenever we get a USB reset, we should revert to full speed mode
514 1 pConfigDscr = pFullSpeedConfigDscr;
515 1 ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
516 1 pOtherConfigDscr = pHighSpeedConfigDscr;
517 1 ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
518 1
519 1 EZUSB_IRQ_CLEAR();
520 1 USBIRQ = bmURES; // Clear URES IRQ
521 1 }
522
523 void ISR_Susp(void) interrupt 0
524 {
525 1 Sleep = TRUE;
526 1 EZUSB_IRQ_CLEAR();
527 1 USBIRQ = bmSUSP;
528 1 }
529
530 void ISR_Highspeed(void) interrupt 0
531 {
532 1 if (EZUSB_HIGHSPEED())
533 1 {
534 2 pConfigDscr = pHighSpeedConfigDscr;
535 2 ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
536 2 pOtherConfigDscr = pFullSpeedConfigDscr;
537 2 ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
538 2 // PA3=0;
539 2 }
540 1 else
541 1
542 1 EZUSB_IRQ_CLEAR();
543 1 USBIRQ = bmHSGRANT;
544 1 }
545 void ISR_Ep0ack(void) interrupt 0
546 {
547 1 }
548 void ISR_Stub(void) interrupt 0
549 {
550 1 }
C51 COMPILER V7.20 FX2_TO_EXTSYNCFIFO 03/12/2008 15:34:04 PAGE 10
551 void ISR_Ep0in(void) interrupt 0
552 {
553 1 }
554 void ISR_Ep0out(void) interrupt 0
555 {
556 1 }
557 void ISR_Ep1in(void) interrupt 0
558 {
559 1 }
560 void ISR_Ep1out(void) interrupt 0
561 {
562 1 }
563 void ISR_Ep2inout(void) interrupt 0
564 {
565 1 }
566 void ISR_Ep4inout(void) interrupt 0
567 {
568 1 }
569 void ISR_Ep6inout(void) interrupt 0
570 {
571 1 }
572 void ISR_Ep8inout(void) interrupt 0
573 {
574 1 }
575 void ISR_Ibn(void) interrupt 0
576 {
577 1 }
578 void ISR_Ep0pingnak(void) interrupt 0
579 {
580 1 }
581 void ISR_Ep1pingnak(void) interrupt 0
582 {
583 1 }
584 void ISR_Ep2pingnak(void) interrupt 0
585 {
586 1 }
587 void ISR_Ep4pingnak(void) interrupt 0
588 {
589 1 }
590 void ISR_Ep6pingnak(void) interrupt 0
591 {
592 1 }
593 void ISR_Ep8pingnak(void) interrupt 0
594 {
595 1 }
596 void ISR_Errorlimit(void) interrupt 0
597 {
598 1 }
599 void ISR_Ep2piderror(void) interrupt 0
600 {
601 1 }
602 void ISR_Ep4piderror(void) interrupt 0
603 {
604 1 }
605 void ISR_Ep6piderror(void) interrupt 0
606 {
607 1 }
608 void ISR_Ep8piderror(void) interrupt 0
609 {
610 1 }
611 void ISR_Ep2pflag(void) interrupt 0
612 {
C51 COMPILER V7.20 FX2_TO_EXTSYNCFIFO 03/12/2008 15:34:04 PAGE 11
613 1 }
614 void ISR_Ep4pflag(void) interrupt 0
615 {
616 1 }
617 void ISR_Ep6pflag(void) interrupt 0
618 {
619 1 }
620 void ISR_Ep8pflag(void) interrupt 0
621 {
622 1 }
623 void ISR_Ep2eflag(void) interrupt 0
624 {
625 1 }
626 void ISR_Ep4eflag(void) interrupt 0
627 {
628 1 }
629 void ISR_Ep6eflag(void) interrupt 0
630 {
631 1 }
632 void ISR_Ep8eflag(void) interrupt 0
633 {
634 1 }
635 void ISR_Ep2fflag(void) interrupt 0
636 {
637 1 }
638 void ISR_Ep4fflag(void) interrupt 0
639 {
640 1 }
641 void ISR_Ep6fflag(void) interrupt 0
642 {
643 1 }
644 void ISR_Ep8fflag(void) interrupt 0
645 {
646 1 }
647 void ISR_GpifComplete(void) interrupt 0
648 {
649 1 }
650 void ISR_GpifWaveform(void) interrupt 0
651 {
652 1 }
653
654
655 /*
656 void Setup_FLOWSTATE_Read ( void )
657 {
658 FLOWSTATE = FlowStates[18]; // 1000 0011b - FSE=1, FS[2:0]=003
659 SYNCDELAY;
660 FLOWEQ0CTL = FlowStates[20]; // CTL1/CTL2 = 0 when flow condition equals zero (data flows)
661 SYNCDELAY;
662 FLOWEQ1CTL = FlowStates[21]; // CTL1/CTL2 = 1 when flow condition equals one (data does not flow)
663 SYNCDELAY;
664 }
665
666 void Setup_FLOWSTATE_Write ( void )
667 {
668 FLOWSTATE = FlowStates[27]; // 1000 0001b - FSE=1, FS[2:0]=001
669 SYNCDELAY;
670 FLOWEQ0CTL = FlowStates[29]; // CTL0 = 0 when flow condition equals zero (data flows)
671 SYNCDELAY;
672 FLOWEQ1CTL = FlowStates[30]; // CTL0 = 1 when flow condition equals one (data does not flow)
673 SYNCDELAY;
674 }
C51 COMPILER V7.20 FX2_TO_EXTSYNCFIFO 03/12/2008 15:34:04 PAGE 12
675
676 void Delay(unsigned int n)
677 {
678 unsigned int i;
679 for(i=0;i<n;i++)
680 ;
681 }
682 */
683 void SendData(BYTE d)
684 { BYTE i;
685 1 DCLK=0;
686 1 for(i=0;i<8;i++)
687 1 {DATA0=(bit)(d&0x01);
688 2 d>>=1;
689 2 DCLK=1;
690 2 DCLK=0;
691 2 }
692 1
693 1 }
694
695 /*
696 void Clock(void)
697 {
698 Delay(10);
699 SK=1;
700 Delay(10);
701 SK=0;
702 }*/
703
704
705
706 /* if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
707 {
708 if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
709 {
710 if ( EXTFIFONOTFULL ) // if the external FIFO is not full
711 {
712 if(enum_high_speed)
713 {
714 SYNCDELAY;
715 GPIFTCB1 = 0x02; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
716 SYNCDELAY;
717 GPIFTCB0 = 0x00;
718 SYNCDELAY;
719 }
720 else
721 {
722 SYNCDELAY;
723 GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
724 SYNCDELAY;
725 GPIFTCB0 = 0x40;
726 SYNCDELAY;
727 }
728 Setup_FLOWSTATE_Write(); // setup FLOWSTATE registers for FIFO Write operation
729 SYNCDELAY;
730 GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
731 SYNCDELAY;
732
733 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
734 {
735 ;
736 }
C51 COMPILER V7.20 FX2_TO_EXTSYNCFIFO 03/12/2008 15:34:04 PAGE 13
737 SYNCDELAY;
738 }
739 }
740 }
741 */
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 1043 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = 2 ----
PDATA SIZE = ---- ----
DATA SIZE = 19 3
IDATA SIZE = ---- ----
BIT SIZE = 2 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -