📄 fifoxactions.htm
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<p align="center"><font face="verdana, arial, helvetica, sans-serif" size="2" color="#000000"><B><a name="SingleXactions"></a>Implementing FIFO
(multiple) Transactions</B></font>
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<font face="Verdana,Arial" size="1" color="#000000">A fully working external FIFO example using GPIF Single transactions has already been discussed, but the bandwidth achieved is miniscule.
This is because there is a lot of firmware overhead involved in launching GPIF Single transactions. With GPIF FIFO transactions, the GPIF engine
directly handles bursts of data, so a higher bandwidth over the physical interface is achievable.<br>
<br><a name="FlowStates"></a></font><font face="Verdana" size="1"><b>Introducing
the Flow State Feature of the GPIF<br><br> </b>In order to efficiently
handle bursts of data and meet burst access timing to the external
FIFO, the flow state feature of the GPIF was utilized for the FIFO
transaction example. The flow state feature makes its debut in the
FX2 GPIF and is a mechanism that allows the GPIF to efficiently
throttle data on and off the bus by using an independent set of
RDYn logic (flow logic) that is separate from the decision point
RDYn logic. Since the flow state feature is an advanced mode of
the GPIF, not every application will need to use the flow state.
However, handling bursts of data to and from an external FIFO shows
the simplest application of the flow state. One very advanced application
of the flow state is in the generation of UDMA waveforms for the
FX2 mass storage reference design firmware.</font>
<p><font face="Verdana" size="1">In any GPIF waveform, there can
only be one flow state, but it can be any of the available non-idle
states (S0朣6). The flow state behavior is controlled by a set of
registers that are specific to the flow state feature (see the FX2
Technical Reference Manual for flow state register details). One
can think of the flow state as being 搊rthogonal⌨️ 快捷键说明
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