altsyncram_7q01.tdf

使用RTL8019芯片进行以太网通讯的VERILOG源代码.

			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a19 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a20 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a21 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a22 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a23 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a24 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a25 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a26 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a27 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a28 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a29 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a30 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a31 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "payload_buffer.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "M4K"
		);
	address_a_wire[12..0]	: WIRE;

BEGIN 
	address_reg_a[].CLK = clock0;
	address_reg_a[].D = address_a[12..12];
	address_reg_a[].ENA = clocken0;
	decode3.data[0..0] = address_a_wire[12..12];
	decode3.enable = wren_a;
	deep_decode.data[0..0] = address_a_wire[12..12];
	deep_decode.enable = clocken0;
	mux2.data[] = ( ram_block1a[31..0].portadataout[0..0]);
	mux2.sel[] = address_reg_a[].Q;
	ram_block1a[31..0].clk0 = clock0;
	ram_block1a[0].ena0 = deep_decode.eq[0..0];
	ram_block1a[1].ena0 = deep_decode.eq[0..0];
	ram_block1a[2].ena0 = deep_decode.eq[0..0];
	ram_block1a[3].ena0 = deep_decode.eq[0..0];
	ram_block1a[4].ena0 = deep_decode.eq[0..0];
	ram_block1a[5].ena0 = deep_decode.eq[0..0];
	ram_block1a[6].ena0 = deep_decode.eq[0..0];
	ram_block1a[7].ena0 = deep_decode.eq[0..0];
	ram_block1a[8].ena0 = deep_decode.eq[0..0];
	ram_block1a[9].ena0 = deep_decode.eq[0..0];
	ram_block1a[10].ena0 = deep_decode.eq[0..0];
	ram_block1a[11].ena0 = deep_decode.eq[0..0];
	ram_block1a[12].ena0 = deep_decode.eq[0..0];
	ram_block1a[13].ena0 = deep_decode.eq[0..0];
	ram_block1a[14].ena0 = deep_decode.eq[0..0];
	ram_block1a[15].ena0 = deep_decode.eq[0..0];
	ram_block1a[16].ena0 = deep_decode.eq[1..1];
	ram_block1a[17].ena0 = deep_decode.eq[1..1];
	ram_block1a[18].ena0 = deep_decode.eq[1..1];
	ram_block1a[19].ena0 = deep_decode.eq[1..1];
	ram_block1a[20].ena0 = deep_decode.eq[1..1];
	ram_block1a[21].ena0 = deep_decode.eq[1..1];
	ram_block1a[22].ena0 = deep_decode.eq[1..1];
	ram_block1a[23].ena0 = deep_decode.eq[1..1];
	ram_block1a[24].ena0 = deep_decode.eq[1..1];
	ram_block1a[25].ena0 = deep_decode.eq[1..1];
	ram_block1a[26].ena0 = deep_decode.eq[1..1];
	ram_block1a[27].ena0 = deep_decode.eq[1..1];
	ram_block1a[28].ena0 = deep_decode.eq[1..1];
	ram_block1a[29].ena0 = deep_decode.eq[1..1];
	ram_block1a[30].ena0 = deep_decode.eq[1..1];
	ram_block1a[31].ena0 = deep_decode.eq[1..1];
	ram_block1a[0].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[1].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[2].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[3].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[4].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[5].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[6].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[7].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[8].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[9].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[10].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[11].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[12].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[13].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[14].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[15].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[16].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[17].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[18].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[19].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[20].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[21].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[22].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[23].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[24].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[25].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[26].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[27].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[28].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[29].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[30].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[31].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[6..6]);
	ram_block1a[7].portadatain[] = ( data_a[7..7]);
	ram_block1a[8].portadatain[] = ( data_a[8..8]);
	ram_block1a[9].portadatain[] = ( data_a[9..9]);
	ram_block1a[10].portadatain[] = ( data_a[10..10]);
	ram_block1a[11].portadatain[] = ( data_a[11..11]);
	ram_block1a[12].portadatain[] = ( data_a[12..12]);
	ram_block1a[13].portadatain[] = ( data_a[13..13]);
	ram_block1a[14].portadatain[] = ( data_a[14..14]);
	ram_block1a[15].portadatain[] = ( data_a[15..15]);
	ram_block1a[16].portadatain[] = ( data_a[0..0]);
	ram_block1a[17].portadatain[] = ( data_a[1..1]);
	ram_block1a[18].portadatain[] = ( data_a[2..2]);
	ram_block1a[19].portadatain[] = ( data_a[3..3]);
	ram_block1a[20].portadatain[] = ( data_a[4..4]);
	ram_block1a[21].portadatain[] = ( data_a[5..5]);
	ram_block1a[22].portadatain[] = ( data_a[6..6]);
	ram_block1a[23].portadatain[] = ( data_a[7..7]);
	ram_block1a[24].portadatain[] = ( data_a[8..8]);
	ram_block1a[25].portadatain[] = ( data_a[9..9]);
	ram_block1a[26].portadatain[] = ( data_a[10..10]);
	ram_block1a[27].portadatain[] = ( data_a[11..11]);
	ram_block1a[28].portadatain[] = ( data_a[12..12]);
	ram_block1a[29].portadatain[] = ( data_a[13..13]);
	ram_block1a[30].portadatain[] = ( data_a[14..14]);
	ram_block1a[31].portadatain[] = ( data_a[15..15]);
	ram_block1a[0].portawe = (decode3.eq[0..0] & byteena_a[0..0]);
	ram_block1a[1].portawe = (decode3.eq[0..0] & byteena_a[0..0]);
	ram_block1a[2].portawe = (decode3.eq[0..0] & byteena_a[0..0]);
	ram_block1a[3].portawe = (decode3.eq[0..0] & byteena_a[0..0]);
	ram_block1a[4].portawe = (decode3.eq[0..0] & byteena_a[0..0]);
	ram_block1a[5].portawe = (decode3.eq[0..0] & byteena_a[0..0]);
	ram_block1a[6].portawe = (decode3.eq[0..0] & byteena_a[0..0]);
	ram_block1a[7].portawe = (decode3.eq[0..0] & byteena_a[0..0]);
	ram_block1a[8].portawe = (decode3.eq[0..0] & byteena_a[1..1]);
	ram_block1a[9].portawe = (decode3.eq[0..0] & byteena_a[1..1]);
	ram_block1a[10].portawe = (decode3.eq[0..0] & byteena_a[1..1]);
	ram_block1a[11].portawe = (decode3.eq[0..0] & byteena_a[1..1]);
	ram_block1a[12].portawe = (decode3.eq[0..0] & byteena_a[1..1]);
	ram_block1a[13].portawe = (decode3.eq[0..0] & byteena_a[1..1]);
	ram_block1a[14].portawe = (decode3.eq[0..0] & byteena_a[1..1]);
	ram_block1a[15].portawe = (decode3.eq[0..0] & byteena_a[1..1]);
	ram_block1a[16].portawe = (decode3.eq[1..1] & byteena_a[0..0]);
	ram_block1a[17].portawe = (decode3.eq[1..1] & byteena_a[0..0]);
	ram_block1a[18].portawe = (decode3.eq[1..1] & byteena_a[0..0]);
	ram_block1a[19].portawe = (decode3.eq[1..1] & byteena_a[0..0]);
	ram_block1a[20].portawe = (decode3.eq[1..1] & byteena_a[0..0]);
	ram_block1a[21].portawe = (decode3.eq[1..1] & byteena_a[0..0]);
	ram_block1a[22].portawe = (decode3.eq[1..1] & byteena_a[0..0]);
	ram_block1a[23].portawe = (decode3.eq[1..1] & byteena_a[0..0]);
	ram_block1a[24].portawe = (decode3.eq[1..1] & byteena_a[1..1]);
	ram_block1a[25].portawe = (decode3.eq[1..1] & byteena_a[1..1]);
	ram_block1a[26].portawe = (decode3.eq[1..1] & byteena_a[1..1]);
	ram_block1a[27].portawe = (decode3.eq[1..1] & byteena_a[1..1]);
	ram_block1a[28].portawe = (decode3.eq[1..1] & byteena_a[1..1]);
	ram_block1a[29].portawe = (decode3.eq[1..1] & byteena_a[1..1]);
	ram_block1a[30].portawe = (decode3.eq[1..1] & byteena_a[1..1]);
	ram_block1a[31].portawe = (decode3.eq[1..1] & byteena_a[1..1]);
	address_a_wire[] = address_a[];
	q_a[] = mux2.result[];
END;
--VALID FILE