rca_cy1c12_board.hier_info

使用RTL8019芯片进行以太网通讯的VERILOG源代码.

|rca_cy1c12_board_top
FLASH_CE_N <= rca_cy1c12_board:inst.select_n_to_the_ext_flash
PLD_CLOCKINPUT[1] => rca_cy1c12_board:inst.clk
PLD_CLEAR_N => rca_cy1c12_board:inst.reset_n
FLASH_D[0] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[0]
FLASH_D[1] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[1]
FLASH_D[2] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[2]
FLASH_D[3] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[3]
FLASH_D[4] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[4]
FLASH_D[5] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[5]
FLASH_D[6] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[6]
FLASH_D[7] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[7]
FLASH_D[8] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[8]
FLASH_D[9] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[9]
FLASH_D[10] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[10]
FLASH_D[11] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[11]
FLASH_D[12] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[12]
FLASH_D[13] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[13]
FLASH_D[14] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[14]
FLASH_D[15] <= rca_cy1c12_board:inst.tri_state_bridge_0_data[15]
FLASH_OE_N <= rca_cy1c12_board:inst.tri_state_bridge_0_readn
FLASH_WE_N <= rca_cy1c12_board:inst.write_n_to_the_ext_flash
SRAM_CE_N <= <VCC>
SRAM_WE_N <= <VCC>
SRAM_OE_N <= <VCC>
FLASH_A[0] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[0]
FLASH_A[1] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[1]
FLASH_A[2] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[2]
FLASH_A[3] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[3]
FLASH_A[4] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[4]
FLASH_A[5] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[5]
FLASH_A[6] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[6]
FLASH_A[7] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[7]
FLASH_A[8] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[8]
FLASH_A[9] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[9]
FLASH_A[10] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[10]
FLASH_A[11] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[11]
FLASH_A[12] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[12]
FLASH_A[13] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[13]
FLASH_A[14] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[14]
FLASH_A[15] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[15]
FLASH_A[16] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[16]
FLASH_A[17] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[17]
FLASH_A[18] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[18]
FLASH_A[19] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[19]
FLASH_A[20] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[20]
FLASH_A[21] <= rca_cy1c12_board:inst.tri_state_bridge_0_address[21]


|rca_cy1c12_board_top|rca_cy1c12_board:inst
clk => clk~0.IN16
reset_n => reset_n_sources.IN1
select_n_to_the_ext_flash <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.select_n_to_the_ext_flash
tri_state_bridge_0_address[0] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[1] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[2] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[3] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[4] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[5] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[6] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[7] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[8] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[9] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[10] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[11] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[12] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[13] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[14] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[15] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[16] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[17] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[18] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[19] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[20] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[21] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_data[0] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[1] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[2] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[3] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[4] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[5] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[6] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[7] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[8] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[9] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[10] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[11] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[12] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[13] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[14] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[15] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_readn <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_readn
write_n_to_the_ext_flash <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.write_n_to_the_ext_flash


|rca_cy1c12_board_top|rca_cy1c12_board:inst|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port
asmi_asmi_control_port_dataavailable => asmi_asmi_control_port_dataavailable_from_sa.DATAIN
asmi_asmi_control_port_endofpacket => asmi_asmi_control_port_endofpacket_from_sa.DATAIN
asmi_asmi_control_port_irq => asmi_asmi_control_port_irq_from_sa.DATAIN
asmi_asmi_control_port_readdata[0] => asmi_asmi_control_port_readdata_from_sa[0].DATAIN
asmi_asmi_control_port_readdata[1] => asmi_asmi_control_port_readdata_from_sa[1].DATAIN
asmi_asmi_control_port_readdata[2] => asmi_asmi_control_port_readdata_from_sa[2].DATAIN
asmi_asmi_control_port_readdata[3] => asmi_asmi_control_port_readdata_from_sa[3].DATAIN
asmi_asmi_control_port_readdata[4] => asmi_asmi_control_port_readdata_from_sa[4].DATAIN
asmi_asmi_control_port_readdata[5] => asmi_asmi_control_port_readdata_from_sa[5].DATAIN
asmi_asmi_control_port_readdata[6] => asmi_asmi_control_port_readdata_from_sa[6].DATAIN
asmi_asmi_control_port_readdata[7] => asmi_asmi_control_port_readdata_from_sa[7].DATAIN
asmi_asmi_control_port_readdata[8] => asmi_asmi_control_port_readdata_from_sa[8].DATAIN
asmi_asmi_control_port_readdata[9] => asmi_asmi_control_port_readdata_from_sa[9].DATAIN
asmi_asmi_control_port_readdata[10] => asmi_asmi_control_port_readdata_from_sa[10].DATAIN
asmi_asmi_control_port_readdata[11] => asmi_asmi_control_port_readdata_from_sa[11].DATAIN
asmi_asmi_control_port_readdata[12] => asmi_asmi_control_port_readdata_from_sa[12].DATAIN
asmi_asmi_control_port_readdata[13] => asmi_asmi_control_port_readdata_from_sa[13].DATAIN
asmi_asmi_control_port_readdata[14] => asmi_asmi_control_port_readdata_from_sa[14].DATAIN
asmi_asmi_control_port_readdata[15] => asmi_asmi_control_port_readdata_from_sa[15].DATAIN
asmi_asmi_control_port_readyfordata => asmi_asmi_control_port_readyfordata_from_sa.DATAIN
clk => d1_asmi_asmi_control_port_end_xfer~reg0.CLK
clk => d1_reasons_to_wait.CLK
cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[2] => asmi_asmi_control_port_address[0].DATAIN
cpu_0_data_master_address_to_slave[3] => asmi_asmi_control_port_address[1].DATAIN
cpu_0_data_master_address_to_slave[4] => asmi_asmi_control_port_address[2].DATAIN
cpu_0_data_master_address_to_slave[5] => reduce_nor~0.IN15
cpu_0_data_master_address_to_slave[6] => reduce_nor~0.IN14
cpu_0_data_master_address_to_slave[7] => reduce_nor~0.IN13
cpu_0_data_master_address_to_slave[8] => reduce_nor~0.IN12
cpu_0_data_master_address_to_slave[9] => reduce_nor~0.IN11
cpu_0_data_master_address_to_slave[10] => reduce_nor~0.IN10
cpu_0_data_master_address_to_slave[11] => reduce_nor~0.IN9
cpu_0_data_master_address_to_slave[12] => reduce_nor~0.IN8
cpu_0_data_master_address_to_slave[13] => reduce_nor~0.IN7
cpu_0_data_master_address_to_slave[14] => reduce_nor~0.IN6
cpu_0_data_master_address_to_slave[15] => reduce_nor~0.IN5
cpu_0_data_master_address_to_slave[16] => reduce_nor~0.IN4
cpu_0_data_master_address_to_slave[17] => reduce_nor~0.IN16
cpu_0_data_master_address_to_slave[18] => reduce_nor~0.IN17
cpu_0_data_master_address_to_slave[19] => reduce_nor~0.IN3
cpu_0_data_master_address_to_slave[20] => reduce_nor~0.IN2
cpu_0_data_master_address_to_slave[21] => reduce_nor~0.IN1
cpu_0_data_master_address_to_slave[22] => reduce_nor~0.IN0
cpu_0_data_master_read => cpu_0_data_master_requests_asmi_asmi_control_port~0.IN0
cpu_0_data_master_read => asmi_asmi_control_port_in_a_read_cycle.IN0
cpu_0_data_master_write => cpu_0_data_master_requests_asmi_asmi_control_port~0.IN1
cpu_0_data_master_write => asmi_asmi_control_port_in_a_write_cycle.IN0
cpu_0_data_master_writedata[0] => asmi_asmi_control_port_writedata[0].DATAIN
cpu_0_data_master_writedata[1] => asmi_asmi_control_port_writedata[1].DATAIN
cpu_0_data_master_writedata[2] => asmi_asmi_control_port_writedata[2].DATAIN
cpu_0_data_master_writedata[3] => asmi_asmi_control_port_writedata[3].DATAIN
cpu_0_data_master_writedata[4] => asmi_asmi_control_port_writedata[4].DATAIN
cpu_0_data_master_writedata[5] => asmi_asmi_control_port_writedata[5].DATAIN
cpu_0_data_master_writedata[6] => asmi_asmi_control_port_writedata[6].DATAIN
cpu_0_data_master_writedata[7] => asmi_asmi_control_port_writedata[7].DATAIN
cpu_0_data_master_writedata[8] => asmi_asmi_control_port_writedata[8].DATAIN
cpu_0_data_master_writedata[9] => asmi_asmi_control_port_writedata[9].DATAIN
cpu_0_data_master_writedata[10] => asmi_asmi_control_port_writedata[10].DATAIN
cpu_0_data_master_writedata[11] => asmi_asmi_control_port_writedata[11].DATAIN
cpu_0_data_master_writedata[12] => asmi_asmi_control_port_writedata[12].DATAIN
cpu_0_data_master_writedata[13] => asmi_asmi_control_port_writedata[13].DATAIN
cpu_0_data_master_writedata[14] => asmi_asmi_control_port_writedata[14].DATAIN
cpu_0_data_master_writedata[15] => asmi_asmi_control_port_writedata[15].DATAIN
cpu_0_data_master_writedata[16] => ~NO_FANOUT~
cpu_0_data_master_writedata[17] => ~NO_FANOUT~
cpu_0_data_master_writedata[18] => ~NO_FANOUT~
cpu_0_data_master_writedata[19] => ~NO_FANOUT~
cpu_0_data_master_writedata[20] => ~NO_FANOUT~
cpu_0_data_master_writedata[21] => ~NO_FANOUT~
cpu_0_data_master_writedata[22] => ~NO_FANOUT~
cpu_0_data_master_writedata[23] => ~NO_FANOUT~
cpu_0_data_master_writedata[24] => ~NO_FANOUT~
cpu_0_data_master_writedata[25] => ~NO_FANOUT~
cpu_0_data_master_writedata[26] => ~NO_FANOUT~
cpu_0_data_master_writedata[27] => ~NO_FANOUT~
cpu_0_data_master_writedata[28] => ~NO_FANOUT~
cpu_0_data_master_writedata[29] => ~NO_FANOUT~
cpu_0_data_master_writedata[30] => ~NO_FANOUT~
cpu_0_data_master_writedata[31] => ~NO_FANOUT~
reset_n => asmi_asmi_control_port_reset_n.DATAIN
reset_n => d1_reasons_to_wait.ACLR
reset_n => d1_asmi_asmi_control_port_end_xfer~reg0.PRESET
asmi_asmi_control_port_address[0] <= cpu_0_data_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_address[1] <= cpu_0_data_master_address_to_slave[3].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_address[2] <= cpu_0_data_master_address_to_slave[4].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_chipselect <= cpu_0_data_master_requests_asmi_asmi_control_port~1.DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_dataavailable_from_sa <= asmi_asmi_control_port_dataavailable.DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_endofpacket_from_sa <= asmi_asmi_control_port_endofpacket.DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_irq_from_sa <= asmi_asmi_control_port_irq.DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_read_n <= asmi_asmi_control_port_in_a_read_cycle.DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[0] <= asmi_asmi_control_port_readdata[0].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[1] <= asmi_asmi_control_port_readdata[1].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[2] <= asmi_asmi_control_port_readdata[2].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[3] <= asmi_asmi_control_port_readdata[3].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[4] <= asmi_asmi_control_port_readdata[4].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[5] <= asmi_asmi_control_port_readdata[5].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[6] <= asmi_asmi_control_port_readdata[6].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[7] <= asmi_asmi_control_port_readdata[7].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[8] <= asmi_asmi_control_port_readdata[8].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[9] <= asmi_asmi_control_port_readdata[9].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[10] <= asmi_asmi_control_port_readdata[10].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[11] <= asmi_asmi_control_port_readdata[11].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[12] <= asmi_asmi_control_port_readdata[12].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[13] <= asmi_asmi_control_port_readdata[13].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[14] <= asmi_asmi_control_port_readdata[14].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readdata_from_sa[15] <= asmi_asmi_control_port_readdata[15].DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_readyfordata_from_sa <= asmi_asmi_control_port_readyfordata.DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE
asmi_asmi_control_port_write_n <= asmi_asmi_control_port_in_a_write_cycle.DB_MAX_OUTPUT_PORT_TYPE