rca_cy1c12_board.hif

使用RTL8019芯片进行以太网通讯的VERILOG源代码.

}
# user_parameter {
lpm_file
rf_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf
}
# end
# entity
altsyncram_dno1
# case_insensitive
# source_file
db|altsyncram_dno1.tdf
1140411181
6
# storage
db|rca_cy1c12_board.(12).cnf
db|rca_cy1c12_board.(12).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
wren_b
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
data_b8
data_b9
data_b10
data_b11
data_b12
data_b13
data_b14
data_b15
data_b16
data_b17
data_b18
data_b19
data_b20
data_b21
data_b22
data_b23
data_b24
data_b25
data_b26
data_b27
data_b28
data_b29
data_b30
data_b31
address_a0
address_a1
address_a2
address_a3
address_a4
address_b0
address_b1
address_b2
address_b3
address_b4
clock0
clock1
clocken0
clocken1
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a20
q_a21
q_a22
q_a23
q_a24
q_a25
q_a26
q_a27
q_a28
q_a29
q_a30
q_a31
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
q_b17
q_b18
q_b19
q_b20
q_b21
q_b22
q_b23
q_b24
q_b25
q_b26
q_b27
q_b28
q_b29
q_b30
q_b31
}
# memory_file {
rf_ram.mif
1143081747
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated
}
# end
# entity
data_RAM_s1_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(13).cnf
db|rca_cy1c12_board.(13).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1
}
# end
# entity
data_RAM
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
data_RAM.v
1143081752
7
# storage
db|rca_cy1c12_board.(14).cnf
db|rca_cy1c12_board.(14).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|data_RAM:the_data_RAM
}
# end
# entity
altsyncram_q201
# case_insensitive
# source_file
db|altsyncram_q201.tdf
1140411182
6
# storage
db|rca_cy1c12_board.(16).cnf
db|rca_cy1c12_board.(16).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
clocken0
byteena_a0
byteena_a1
byteena_a2
byteena_a3
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a20
q_a21
q_a22
q_a23
q_a24
q_a25
q_a26
q_a27
q_a28
q_a29
q_a30
q_a31
}
# memory_file {
data_RAM.hex
1143081752
}
# hierarchies {
rca_cy1c12_board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_q201:auto_generated
}
# end
# entity
firmware_ROM_s1_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(17).cnf
db|rca_cy1c12_board.(17).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1
}
# end
# entity
firmware_ROM
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
firmware_ROM.v
1143081751
7
# storage
db|rca_cy1c12_board.(18).cnf
db|rca_cy1c12_board.(18).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|firmware_ROM:the_firmware_ROM
}
# end
# entity
jtag_uart_0_avalon_jtag_slave_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(21).cnf
db|rca_cy1c12_board.(21).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave
}
# end
# entity
jtag_uart_0
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
1143081755
7
# storage
db|rca_cy1c12_board.(22).cnf
db|rca_cy1c12_board.(22).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0
}
# end
# entity
jtag_uart_0_scfifo_w
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
1143081755
7
# storage
db|rca_cy1c12_board.(23).cnf
db|rca_cy1c12_board.(23).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w
}
# end
# entity
altsyncram_bhc1
# case_insensitive
# source_file
db|altsyncram_bhc1.tdf
1140411184
6
# storage
db|rca_cy1c12_board.(30).cnf
db|rca_cy1c12_board.(30).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
clock0
clock1
clocken1
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
wren_a
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
none
0
}
# hierarchies {
rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1to:auto_generated|a_dpfifo_83p:dpfifo|dpram_75p:FIFOram|altsyncram_bhc1:altsyncram1
rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1to:auto_generated|a_dpfifo_83p:dpfifo|dpram_75p:FIFOram|altsyncram_bhc1:altsyncram1
}
# end
# entity
jtag_uart_0_scfifo_r
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
1143081755
7
# storage
db|rca_cy1c12_board.(32).cnf
db|rca_cy1c12_board.(32).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r
}
# end
# entity
payload_buffer_s1_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(34).cnf
db|rca_cy1c12_board.(34).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1
}
# end
# entity
payload_buffer
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
payload_buffer.v
1143081754
7
# storage
db|rca_cy1c12_board.(35).cnf
db|rca_cy1c12_board.(35).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|payload_buffer:the_payload_buffer
}
# end
# entity
altsyncram_7q01
# case_insensitive
# source_file
db|altsyncram_7q01.tdf
1140411186
6
# storage
db|rca_cy1c12_board.(37).cnf
db|rca_cy1c12_board.(37).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_a11
address_a12
clock0
clocken0
byteena_a0
byteena_a1
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
}
# memory_file {
payload_buffer.hex
1143081753
}
# hierarchies {
rca_cy1c12_board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_7q01:auto_generated
}
# end
# entity
sysid_control_slave_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(40).cnf
db|rca_cy1c12_board.(40).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|sysid_control_slave_arbitrator:the_sysid_control_slave
}
# end
# entity
sysid
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sysid.v
1143081757
7
# storage
db|rca_cy1c12_board.(41).cnf
db|rca_cy1c12_board.(41).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|sysid:the_sysid
}
# end
# entity
tri_state_bridge_0_avalon_slave_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(42).cnf
db|rca_cy1c12_board.(42).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave
}
# end
# entity
rca_cy1c12_board_reset_clk_domain_synch_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(43).cnf
db|rca_cy1c12_board.(43).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch
}
# end
# complete