rca_cy1c12_board.hif

使用RTL8019芯片进行以太网通讯的VERILOG源代码.

DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_7q01
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
byteena_a
byteena_a
clock0
clocken0
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
rca_cy1c12_board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram
}
# end
# entity
decode_fga
# case_insensitive
# source_file
db|decode_fga.tdf
1140411186
6
# storage
db|rca_cy1c12_board.(38).cnf
db|rca_cy1c12_board.(38).cnf
# used_port {
data0
enable
eq0
eq1
}
# hierarchies {
rca_cy1c12_board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_7q01:auto_generated|decode_fga:decode3
rca_cy1c12_board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_7q01:auto_generated|decode_fga:deep_decode
}
# end
# entity
mux_ecb
# case_insensitive
# source_file
db|mux_ecb.tdf
1140411186
6
# storage
db|rca_cy1c12_board.(39).cnf
db|rca_cy1c12_board.(39).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data20
data21
data22
data23
data24
data25
data26
data27
data28
data29
data30
data31
sel0
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
result11
result12
result13
result14
result15
}
# hierarchies {
rca_cy1c12_board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_7q01:auto_generated|mux_ecb:mux2
}
# end
# entity
sld_hub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(44).cnf
db|rca_cy1c12_board.(44).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
2
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone
PARAMETER_UNKNOWN
USR
n_nodes
1
PARAMETER_UNKNOWN
USR
n_sel_bits
1
PARAMETER_UNKNOWN
USR
n_node_ir_bits
4
PARAMETER_UNKNOWN
USR
node_info
00001100000000000110111000000000
PARAMETER_BIN
USR
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
}
# end
# entity
sld_jtag_state_machine
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(45).cnf
db|rca_cy1c12_board.(45).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|rca_cy1c12_board.(46).cnf
db|rca_cy1c12_board.(46).cnf
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
enable
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
c:|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
}
# end
# entity
lpm_decode
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_decode.tdf
1114012450
6
# storage
db|rca_cy1c12_board.(47).cnf
db|rca_cy1c12_board.(47).cnf
# user_parameter {
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DECODES
8
PARAMETER_DEC
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_9ie
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq7
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
c:|altera|quartus50|libraries|megafunctions|declut.inc
1107574136
c:|altera|quartus50|libraries|megafunctions|altshift.inc
1107573438
c:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
}
# end
# entity
decode_9ie
# case_insensitive
# source_file
db|decode_9ie.tdf
1140411192
6
# storage
db|rca_cy1c12_board.(48).cnf
db|rca_cy1c12_board.(48).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(49).cnf
db|rca_cy1c12_board.(49).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
1
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(50).cnf
db|rca_cy1c12_board.(50).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
5
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(51).cnf
db|rca_cy1c12_board.(51).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
4
PARAMETER_DEC
USR
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(52).cnf
db|rca_cy1c12_board.(52).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
64
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# end
# entity
rca_cy1c12_board_top
# case_insensitive
# source_file
rca_cy1c12_board_top.bdf
1143081783
23
# storage
db|rca_cy1c12_board.(0).cnf
db|rca_cy1c12_board.(0).cnf
# hierarchies {
|
}
# end
# entity
rca_cy1c12_board
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(1).cnf
db|rca_cy1c12_board.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst
}
# end
# entity
asmi_asmi_control_port_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(2).cnf
db|rca_cy1c12_board.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port
}
# end
# entity
asmi
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1143081758
7
# storage
db|rca_cy1c12_board.(3).cnf
db|rca_cy1c12_board.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|asmi:the_asmi
}
# end
# entity
asmi_sub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1143081758
7
# storage
db|rca_cy1c12_board.(4).cnf
db|rca_cy1c12_board.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub
}
# end
# entity
tornado_asmi_atom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1143081758
7
# storage
db|rca_cy1c12_board.(5).cnf
db|rca_cy1c12_board.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|asmi:the_asmi|tornado_asmi_atom:the_tornado_asmi_atom
}
# end
# entity
cpu_0_data_master_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(6).cnf
db|rca_cy1c12_board.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master
}
# end
# entity
cpu_0_instruction_master_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1143081769
7
# storage
db|rca_cy1c12_board.(7).cnf
db|rca_cy1c12_board.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master
}
# end
# entity
cpu_0
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
1143081749
7
# storage
db|rca_cy1c12_board.(8).cnf
db|rca_cy1c12_board.(8).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0:the_cpu_0
}
# end
# entity
cpu_0_test_bench
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_test_bench.v
1143081748
7
# storage
db|rca_cy1c12_board.(9).cnf
db|rca_cy1c12_board.(9).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench
}
# end
# entity
cpu_0_rf_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
1143081749
7
# storage
db|rca_cy1c12_board.(10).cnf
db|rca_cy1c12_board.(10).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF