mux_ecb.tdf

使用RTL8019芯片进行以太网通讯的VERILOG源代码.

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=2 LPM_WIDTH=16 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 16 
SUBDESIGN mux_ecb
( 
	data[31..0]	:	input;
	result[15..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[15..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data232w[1..0]	: WIRE;
	w_data246w[1..0]	: WIRE;
	w_data258w[1..0]	: WIRE;
	w_data270w[1..0]	: WIRE;
	w_data282w[1..0]	: WIRE;
	w_data294w[1..0]	: WIRE;
	w_data306w[1..0]	: WIRE;
	w_data318w[1..0]	: WIRE;
	w_data330w[1..0]	: WIRE;
	w_data342w[1..0]	: WIRE;
	w_data354w[1..0]	: WIRE;
	w_data366w[1..0]	: WIRE;
	w_data378w[1..0]	: WIRE;
	w_data390w[1..0]	: WIRE;
	w_data402w[1..0]	: WIRE;
	w_data414w[1..0]	: WIRE;
	w_result233w	: WIRE;
	w_result239w	: WIRE;
	w_result247w	: WIRE;
	w_result253w	: WIRE;
	w_result259w	: WIRE;
	w_result265w	: WIRE;
	w_result271w	: WIRE;
	w_result277w	: WIRE;
	w_result283w	: WIRE;
	w_result289w	: WIRE;
	w_result295w	: WIRE;
	w_result301w	: WIRE;
	w_result307w	: WIRE;
	w_result313w	: WIRE;
	w_result319w	: WIRE;
	w_result325w	: WIRE;
	w_result331w	: WIRE;
	w_result337w	: WIRE;
	w_result343w	: WIRE;
	w_result349w	: WIRE;
	w_result355w	: WIRE;
	w_result361w	: WIRE;
	w_result367w	: WIRE;
	w_result373w	: WIRE;
	w_result379w	: WIRE;
	w_result385w	: WIRE;
	w_result391w	: WIRE;
	w_result397w	: WIRE;
	w_result403w	: WIRE;
	w_result409w	: WIRE;
	w_result415w	: WIRE;
	w_result421w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result415w, w_result403w, w_result391w, w_result379w, w_result367w, w_result355w, w_result343w, w_result331w, w_result319w, w_result307w, w_result295w, w_result283w, w_result271w, w_result259w, w_result247w, w_result233w);
	sel_node[] = ( sel[0..0]);
	w_data232w[] = ( data[16..16], data[0..0]);
	w_data246w[] = ( data[17..17], data[1..1]);
	w_data258w[] = ( data[18..18], data[2..2]);
	w_data270w[] = ( data[19..19], data[3..3]);
	w_data282w[] = ( data[20..20], data[4..4]);
	w_data294w[] = ( data[21..21], data[5..5]);
	w_data306w[] = ( data[22..22], data[6..6]);
	w_data318w[] = ( data[23..23], data[7..7]);
	w_data330w[] = ( data[24..24], data[8..8]);
	w_data342w[] = ( data[25..25], data[9..9]);
	w_data354w[] = ( data[26..26], data[10..10]);
	w_data366w[] = ( data[27..27], data[11..11]);
	w_data378w[] = ( data[28..28], data[12..12]);
	w_data390w[] = ( data[29..29], data[13..13]);
	w_data402w[] = ( data[30..30], data[14..14]);
	w_data414w[] = ( data[31..31], data[15..15]);
	w_result233w = w_result239w;
	w_result239w = ((sel_node[] & w_data232w[1..1]) # ((! sel_node[]) & w_data232w[0..0]));
	w_result247w = w_result253w;
	w_result253w = ((sel_node[] & w_data246w[1..1]) # ((! sel_node[]) & w_data246w[0..0]));
	w_result259w = w_result265w;
	w_result265w = ((sel_node[] & w_data258w[1..1]) # ((! sel_node[]) & w_data258w[0..0]));
	w_result271w = w_result277w;
	w_result277w = ((sel_node[] & w_data270w[1..1]) # ((! sel_node[]) & w_data270w[0..0]));
	w_result283w = w_result289w;
	w_result289w = ((sel_node[] & w_data282w[1..1]) # ((! sel_node[]) & w_data282w[0..0]));
	w_result295w = w_result301w;
	w_result301w = ((sel_node[] & w_data294w[1..1]) # ((! sel_node[]) & w_data294w[0..0]));
	w_result307w = w_result313w;
	w_result313w = ((sel_node[] & w_data306w[1..1]) # ((! sel_node[]) & w_data306w[0..0]));
	w_result319w = w_result325w;
	w_result325w = ((sel_node[] & w_data318w[1..1]) # ((! sel_node[]) & w_data318w[0..0]));
	w_result331w = w_result337w;
	w_result337w = ((sel_node[] & w_data330w[1..1]) # ((! sel_node[]) & w_data330w[0..0]));
	w_result343w = w_result349w;
	w_result349w = ((sel_node[] & w_data342w[1..1]) # ((! sel_node[]) & w_data342w[0..0]));
	w_result355w = w_result361w;
	w_result361w = ((sel_node[] & w_data354w[1..1]) # ((! sel_node[]) & w_data354w[0..0]));
	w_result367w = w_result373w;
	w_result373w = ((sel_node[] & w_data366w[1..1]) # ((! sel_node[]) & w_data366w[0..0]));
	w_result379w = w_result385w;
	w_result385w = ((sel_node[] & w_data378w[1..1]) # ((! sel_node[]) & w_data378w[0..0]));
	w_result391w = w_result397w;
	w_result397w = ((sel_node[] & w_data390w[1..1]) # ((! sel_node[]) & w_data390w[0..0]));
	w_result403w = w_result409w;
	w_result409w = ((sel_node[] & w_data402w[1..1]) # ((! sel_node[]) & w_data402w[0..0]));
	w_result415w = w_result421w;
	w_result421w = ((sel_node[] & w_data414w[1..1]) # ((! sel_node[]) & w_data414w[0..0]));
END;
--VALID FILE