rca_cy1c12_board.tan.qmsg

使用RTL8019芯片进行以太网通讯的VERILOG源代码.

{ "Info" "ITDB_TSU_RESULT" "rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[1\] FLASH_D\[1\] PLD_CLOCKINPUT\[1\] 3.440 ns register " "Info: tsu for register \"rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[1\]\" (data pin = \"FLASH_D\[1\]\", clock pin = \"PLD_CLOCKINPUT\[1\]\") is 3.440 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.547 ns + Longest pin register " "Info: + Longest pin to register delay is 5.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FLASH_D\[1\] 1 PIN PIN_121 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_121; Fanout = 1; PIN Node = 'FLASH_D\[1\]'" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[1] } "NODE_NAME" } "" } } { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.547 ns) 5.547 ns rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[1\] 2 REG IOC_X53_Y1_N1 1 " "Info: 2: + IC(0.000 ns) + CELL(5.547 ns) = 5.547 ns; Loc. = IOC_X53_Y1_N1; Fanout = 1; REG Node = 'rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[1\]'" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "5.547 ns" { FLASH_D[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] } "NODE_NAME" } "" } } { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 2573 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.547 ns 100.00 % " "Info: Total cell delay = 5.547 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "5.547 ns" { FLASH_D[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.547 ns" { FLASH_D[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] } { 0.000ns 0.000ns } { 0.000ns 5.547ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.517 ns + " "Info: + Micro setup delay of destination is 0.517 ns" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 2573 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLD_CLOCKINPUT\[1\] destination 2.624 ns - Shortest register " "Info: - Shortest clock path from clock \"PLD_CLOCKINPUT\[1\]\" to destination register is 2.624 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns PLD_CLOCKINPUT\[1\] 1 CLK PIN_153 1595 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1595; CLK Node = 'PLD_CLOCKINPUT\[1\]'" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { PLD_CLOCKINPUT[1] } "NODE_NAME" } "" } } { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 64 408 576 80 "PLD_CLOCKINPUT\[1\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.224 ns) 2.624 ns rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[1\] 2 REG IOC_X53_Y1_N1 1 " "Info: 2: + IC(0.931 ns) + CELL(0.224 ns) = 2.624 ns; Loc. = IOC_X53_Y1_N1; Fanout = 1; REG Node = 'rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[1\]'" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "1.155 ns" { PLD_CLOCKINPUT[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] } "NODE_NAME" } "" } } { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 2573 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.693 ns 64.52 % " "Info: Total cell delay = 1.693 ns ( 64.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns 35.48 % " "Info: Total interconnect delay = 0.931 ns ( 35.48 % )" {  } {  } 0}  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "2.624 ns" { PLD_CLOCKINPUT[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.624 ns" { PLD_CLOCKINPUT[1] PLD_CLOCKINPUT[1]~out0 rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.224ns } } }  } 0}  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "5.547 ns" { FLASH_D[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.547 ns" { FLASH_D[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] } { 0.000ns 0.000ns } { 0.000ns 5.547ns } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "2.624 ns" { PLD_CLOCKINPUT[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.624 ns" { PLD_CLOCKINPUT[1] PLD_CLOCKINPUT[1]~out0 rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.224ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "PLD_CLOCKINPUT\[1\] FLASH_D\[6\] rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[6\] 4.963 ns register " "Info: tco from clock \"PLD_CLOCKINPUT\[1\]\" to destination pin \"FLASH_D\[6\]\" through register \"rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[6\]\" is 4.963 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLD_CLOCKINPUT\[1\] source 2.851 ns + Longest register " "Info: + Longest clock path from clock \"PLD_CLOCKINPUT\[1\]\" to source register is 2.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns PLD_CLOCKINPUT\[1\] 1 CLK PIN_153 1595 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1595; CLK Node = 'PLD_CLOCKINPUT\[1\]'" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { PLD_CLOCKINPUT[1] } "NODE_NAME" } "" } } { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 64 408 576 80 "PLD_CLOCKINPUT\[1\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.163 ns) + CELL(0.219 ns) 2.851 ns rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[6\] 2 REG IOC_X32_Y0_N0 1 " "Info: 2: + IC(1.163 ns) + CELL(0.219 ns) = 2.851 ns; Loc. = IOC_X32_Y0_N0; Fanout = 1; REG Node = 'rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[6\]'" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "1.382 ns" { PLD_CLOCKINPUT[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] } "NODE_NAME" } "" } } { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 2616 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.688 ns 59.21 % " "Info: Total cell delay = 1.688 ns ( 59.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.163 ns 40.79 % " "Info: Total interconnect delay = 1.163 ns ( 40.79 % )" {  } {  } 0}  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "2.851 ns" { PLD_CLOCKINPUT[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.851 ns" { PLD_CLOCKINPUT[1] PLD_CLOCKINPUT[1]~out0 rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] } { 0.000ns 0.000ns 1.163ns } { 0.000ns 1.469ns 0.219ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 2616 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.903 ns + Longest register pin " "Info: + Longest register to pin delay is 1.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[6\] 1 REG IOC_X32_Y0_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = IOC_X32_Y0_N0; Fanout = 1; REG Node = 'rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|d1_outgoing_tri_state_bridge_0_data\[6\]'" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] } "NODE_NAME" } "" } } { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 2616 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.903 ns) 1.903 ns FLASH_D\[6\] 2 PIN PIN_101 0 " "Info: 2: + IC(0.000 ns) + CELL(1.903 ns) = 1.903 ns; Loc. = PIN_101; Fanout = 0; PIN Node = 'FLASH_D\[6\]'" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "1.903 ns" { rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] FLASH_D[6] } "NODE_NAME" } "" } } { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.903 ns 100.00 % " "Info: Total cell delay = 1.903 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "1.903 ns" { rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] FLASH_D[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.903 ns" { rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] FLASH_D[6] } { 0.000ns 0.000ns } { 0.000ns 1.903ns } } }  } 0}  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "2.851 ns" { PLD_CLOCKINPUT[1] rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.851 ns" { PLD_CLOCKINPUT[1] PLD_CLOCKINPUT[1]~out0 rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] } { 0.000ns 0.000ns 1.163ns } { 0.000ns 1.469ns 0.219ns } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "1.903 ns" { rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] FLASH_D[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.903 ns" { rca_cy1c12_board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6] FLASH_D[6] } { 0.000ns 0.000ns } { 0.000ns 1.903ns } } }  } 0}