rca_cy1c12_board.map.qmsg

使用RTL8019芯片进行以太网通讯的VERILOG源代码.

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_6_is_x cpu_0_test_bench.v(239) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(239): object \"av_ld_data_aligned_unfiltered_6_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/cpu_0_test_bench.v" 239 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_7_is_x cpu_0_test_bench.v(240) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(240): object \"av_ld_data_aligned_unfiltered_7_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/cpu_0_test_bench.v" 240 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_8_is_x cpu_0_test_bench.v(241) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(241): object \"av_ld_data_aligned_unfiltered_8_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/cpu_0_test_bench.v" 241 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_9_is_x cpu_0_test_bench.v(242) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(242): object \"av_ld_data_aligned_unfiltered_9_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/cpu_0_test_bench.v" 242 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 cpu_0_test_bench.v(249) " "Warning: Verilog HDL assignment warning at cpu_0_test_bench.v(249): truncated value with size 32 to match size of target (1)" {  } { { "cpu_0_test_bench.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/cpu_0_test_bench.v" 249 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "cpu_0_test_bench.v(250) " "Warning: (10037) Verilog HDL or VHDL warning at cpu_0_test_bench.v(250): condition expression evaluates to a constant" {  } { { "cpu_0_test_bench.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/cpu_0_test_bench.v" 250 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_rf_module rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf " "Info: Elaborating entity \"cpu_0_rf_module\" for hierarchy \"rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\"" {  } { { "cpu_0.v" "cpu_0_rf" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/cpu_0.v" 1136 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/cpu_0.v" 66 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dno1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_dno1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dno1 " "Info: Found entity 1: altsyncram_dno1" {  } { { "db/altsyncram_dno1.tdf" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/altsyncram_dno1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_dno1 rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram\|altsyncram_dno1:auto_generated " "Info: Elaborating entity \"altsyncram_dno1\" for hierarchy \"rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram\|altsyncram_dno1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_RAM_s1_arbitrator rca_cy1c12_board:inst\|data_RAM_s1_arbitrator:the_data_RAM_s1 " "Info: Elaborating entity \"data_RAM_s1_arbitrator\" for hierarchy \"rca_cy1c12_board:inst\|data_RAM_s1_arbitrator:the_data_RAM_s1\"" {  } { { "rca_cy1c12_board.v" "the_data_RAM_s1" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3591 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(991) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(991): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 991 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rca_cy1c12_board.v(992) " "Warning: (10037) Verilog HDL or VHDL warning at rca_cy1c12_board.v(992): condition expression evaluates to a constant" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 992 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(1006) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1006): truncated value with size 32 to match size of target (2)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1006 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(1009) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1009): truncated value with size 32 to match size of target (2)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1009 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(1027) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1027): truncated value with size 32 to match size of target (2)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1027 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(1037) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1037): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1037 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(1053) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1053): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1053 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rca_cy1c12_board.v(1054) " "Warning: (10037) Verilog HDL or VHDL warning at rca_cy1c12_board.v(1054): condition expression evaluates to a constant" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1054 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(1055) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1055): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1055 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 rca_cy1c12_board.v(1071) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1071): truncated value with size 2 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1071 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(1077) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1077): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1077 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rca_cy1c12_board.v(1078) " "Warning: (10037) Verilog HDL or VHDL warning at rca_cy1c12_board.v(1078): condition expression evaluates to a constant" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1078 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(1097) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1097): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1097 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rca_cy1c12_board.v(1098) " "Warning: (10037) Verilog HDL or VHDL warning at rca_cy1c12_board.v(1098): condition expression evaluates to a constant" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1098 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(1099) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1099): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1099 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 rca_cy1c12_board.v(1111) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1111): truncated value with size 2 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1111 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(1117) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1117): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1117 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rca_cy1c12_board.v(1118) " "Warning: (10037) Verilog HDL or VHDL warning at rca_cy1c12_board.v(1118): condition expression evaluates to a constant" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1118 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(1157) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1157): truncated value with size 32 to match size of target (2)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1157 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(1168) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(1168): truncated value with size 32 to match size of target (2)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1168 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(1174) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.