rca_cy1c12_board.fit.qmsg

使用RTL8019芯片进行以太网通讯的VERILOG源代码.

{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "PLD_CLEAR_N " "Info: Node PLD_CLEAR_N uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_out " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_out -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch|data_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_out" } } } } { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3189 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch|data_out } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_in_d1 " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_in_d1 -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch|data_in_d1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_in_d1" } } } } { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3194 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch|data_in_d1 } "NODE_NAME" } }  } 0}  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { PLD_CLEAR_N } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "PLD_CLEAR_N" } } } } { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 80 408 576 96 "PLD_CLEAR_N" "" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { PLD_CLEAR_N } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[8\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[8\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[8\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 186 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[9\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[9\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[9\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 186 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|count\[9\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|count\[9\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|count\[9\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 210 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[3\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[3\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[3\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 186 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[7\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[7\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[7\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 186 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[4\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[4\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[4\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 186 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|count\[0\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|count\[0\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|count\[0\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 210 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[7\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[7\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[7\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 213 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[5\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[5\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[5\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 213 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 200 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[2\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[2\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[2\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 213 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[6\] " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[6\] -- routed using non-global resources" {  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|wdata\[6\]" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 213 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[6] } "NODE_NAME" } }  } 0}  } { { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } }  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "4 " "Warning: The following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_CE_N VCC " "Info: Pin SRAM_CE_N has VCC driving its datain port" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 304 736 912 320 "SRAM_CE_N" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { SRAM_CE_N } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { SRAM_CE_N } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_WE_N VCC " "Info: Pin SRAM_WE_N has VCC driving its datain port" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 320 736 912 336 "SRAM_WE_N" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { SRAM_WE_N } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { SRAM_WE_N } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_OE_N VCC " "Info: Pin SRAM_OE_N has VCC driving its datain port" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 336 736 912 352 "SRAM_OE_N" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { SRAM_OE_N } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { SRAM_OE_N } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_A\[0\] GND " "Info: Pin FLASH_A\[0\] has GND driving its datain port" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 128 928 1104 144 "FLASH_A\[21..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_A\[0\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_A[0] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_A[0] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: The following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|ext_flash_s1_in_a_write_cycle " "Info: The following pins have the same output enable: rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|ext_flash_s1_in_a_write_cycle" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[15\] LVTTL " "Info: Type bidirectional pin FLASH_D\[15\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[15\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[15] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[15] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[14\] LVTTL " "Info: Type bidirectional pin FLASH_D\[14\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[14\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[14] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[14] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[13\] LVTTL " "Info: Type bidirectional pin FLASH_D\[13\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[13\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[13] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[13] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[12\] LVTTL " "Info: Type bidirectional pin FLASH_D\[12\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[12\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[12] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[12] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[11\] LVTTL " "Info: Type bidirectional pin FLASH_D\[11\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[11\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[11] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[11] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[10\] LVTTL " "Info: Type bidirectional pin FLASH_D\[10\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[10\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[10] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[10] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[9\] LVTTL " "Info: Type bidirectional pin FLASH_D\[9\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[9\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[9] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[8\] LVTTL " "Info: Type bidirectional pin FLASH_D\[8\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[8\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[8] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[7\] LVTTL " "Info: Type bidirectional pin FLASH_D\[7\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[7\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[7] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[6\] LVTTL " "Info: Type bidirectional pin FLASH_D\[6\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[6\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[6] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[5\] LVTTL " "Info: Type bidirectional pin FLASH_D\[5\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/b