rca_cy1c12_board.fit.qmsg

使用RTL8019芯片进行以太网通讯的VERILOG源代码.

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_CANT_PACK_FAST_REGISTER_IO" "FLASH_A\[0\] " "Warning: Can't pack node FLASH_A\[0\] to I/O pin" { { "Warning" "WFSAC_FSAC_REGISTER_PACKING_NO_OUTPUT_IO_REGISTER_CONNECTION" "FLASH_A\[0\] " "Warning: Can't pack node FLASH_A\[0\] -- no packable connection between output pin and register" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 128 928 1104 144 "FLASH_A\[21..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_A\[0\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_A[0] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_A[0] } "NODE_NAME" } }  } 0}  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 128 928 1104 144 "FLASH_A\[21..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_A\[0\]" } } } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_A[0] } "NODE_NAME" } "" } } { "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C12/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_A[0] } "NODE_NAME" } }  } 2}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 2 42 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 22 27 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 22 total pin(s) used --  27 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 27 15 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 27 total pin(s) used --  15 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}