i2c_altera.map.qmsg

视频采集

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(112) " "Warning: Verilog HDL assignment warning at blank_gen.v(112): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 112 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(115) " "Warning: Verilog HDL assignment warning at blank_gen.v(115): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 115 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(117) " "Warning: Verilog HDL assignment warning at blank_gen.v(117): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 117 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "receiver mesure_card_top:inst5\|receiver:receiver1 " "Info: Elaborating entity \"receiver\" for hierarchy \"mesure_card_top:inst5\|receiver:receiver1\"" {  } { { "mesure_card_top.v" "receiver1" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 199 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "ODD_STATE receiver.v(98) " "Warning: Verilog HDL warning at receiver.v(98): port \"ODD_STATE\" was previously declared with different range" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 98 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 receiver.v(102) " "Warning: Verilog HDL assignment warning at receiver.v(102): truncated value with size 32 to match size of target (3)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 102 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(103) " "Warning: Verilog HDL assignment warning at receiver.v(103): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 103 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 receiver.v(111) " "Warning: (10271) Verilog HDL Case Statement warning at receiver.v(111): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 111 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 receiver.v(115) " "Warning: (10271) Verilog HDL Case Statement warning at receiver.v(115): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 115 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 receiver.v(119) " "Warning: (10271) Verilog HDL Case Statement warning at receiver.v(119): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 119 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 receiver.v(123) " "Warning: (10271) Verilog HDL Case Statement warning at receiver.v(123): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "receiver.v(106) " "Warning: (10270) Verilog HDL statement warning at receiver.v(106): incomplete Case Statement has no default case item" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 106 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(137) " "Warning: Verilog HDL assignment warning at receiver.v(137): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(139) " "Warning: Verilog HDL assignment warning at receiver.v(139): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 receiver.v(167) " "Warning: Verilog HDL assignment warning at receiver.v(167): truncated value with size 32 to match size of target (10)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 167 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 receiver.v(170) " "Warning: Verilog HDL assignment warning at receiver.v(170): truncated value with size 32 to match size of target (10)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 170 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 receiver.v(172) " "Warning: Verilog HDL assignment warning at receiver.v(172): truncated value with size 32 to match size of target (10)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 172 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 receiver.v(175) " "Warning: Verilog HDL assignment warning at receiver.v(175): truncated value with size 32 to match size of target (10)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 175 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 receiver.v(180) " "Warning: Verilog HDL assignment warning at receiver.v(180): truncated value with size 32 to match size of target (9)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 180 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 receiver.v(183) " "Warning: Verilog HDL assignment warning at receiver.v(183): truncated value with size 32 to match size of target (9)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 183 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 receiver.v(185) " "Warning: Verilog HDL assignment warning at receiver.v(185): truncated value with size 32 to match size of target (9)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 185 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 receiver.v(188) " "Warning: Verilog HDL assignment warning at receiver.v(188): truncated value with size 32 to match size of target (9)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 188 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 receiver.v(195) " "Warning: Verilog HDL assignment warning at receiver.v(195): truncated value with size 32 to match size of target (8)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 195 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 receiver.v(197) " "Warning: Verilog HDL assignment warning at receiver.v(197): truncated value with size 32 to match size of target (8)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 197 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 receiver.v(199) " "Warning: Verilog HDL assignment warning at receiver.v(199): truncated value with size 32 to match size of target (8)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 199 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(204) " "Warning: Verilog HDL assignment warning at receiver.v(204): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 204 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(206) " "Warning: Verilog HDL assignment warning at receiver.v(206): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 206 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(208) " "Warning: Verilog HDL assignment warning at receiver.v(208): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 208 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(213) " "Warning: Verilog HDL assignment warning at receiver.v(213): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 213 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(215) " "Warning: Verilog HDL assignment warning at receiver.v(215): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 215 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(217) " "Warning: Verilog HDL assignment warning at receiver.v(217): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 217 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(222) " "Warning: Verilog HDL assignment warning at receiver.v(222): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 222 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(224) " "Warning: Verilog HDL assignment warning at receiver.v(224): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 224 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(226) " "Warning: Verilog HDL assignment warning at receiver.v(226): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 226 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(231) " "Warning: Verilog HDL assignment warning at receiver.v(231): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 231 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(233) " "Warning: Verilog HDL assignment warning at receiver.v(233): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 233 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(235) " "Warning: Verilog HDL assignment warning at receiver.v(235): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 235 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(240) " "Warning: Verilog HDL assignment warning at receiver.v(240): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 240 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(242) " "Warning: Verilog HDL assignment warning at receiver.v(242): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 242 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 receiver.v(244) " "Warning: Verilog HDL assignment warning at receiver.v(244): truncated value with size 32 to match size of target (1)" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 244 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram1k_8to256_32 mesure_card_top:inst5\|ram1k_8to256_32:ram_r0 " "Info: Elaborating entity \"ram1k_8to256_32\" for hierarchy \"mesure_card_top:inst5\|ram1k_8to256_32:ram_r0\"" {  } { { "mesure_card_top.v" "ram_r0" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 212 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mesure_card_top:inst5\|ram1k_8to256_32:ram_r0\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"mesure_card_top:inst5\|ram1k_8to256_32:ram_r0\|altsyncram:altsyncram_component\"" {  } { { "ram1k_8to256_32.v" "altsyncram_component" { Text "D:/RedLogic/VBuffer/ram1k_8to256_32.v" 85 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_l951.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_l951.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_l951 " "Info: Found entity 1: altsync