i2c_altera.map.qmsg

视频采集

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mesure_card_top.v(517) " "Warning: Verilog HDL assignment warning at mesure_card_top.v(517): truncated value with size 32 to match size of target (1)" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 517 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "sdram_clk mesure_card_top.v(77) " "Warning: Output port \"sdram_clk\" at mesure_card_top.v(77) has no driver" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 77 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "image_NTSC mesure_card_top:inst5\|image_NTSC:source " "Info: Elaborating entity \"image_NTSC\" for hierarchy \"mesure_card_top:inst5\|image_NTSC:source\"" {  } { { "mesure_card_top.v" "source" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 147 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 image_ntsc.v(62) " "Warning: Verilog HDL assignment warning at image_ntsc.v(62): truncated value with size 32 to match size of target (11)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 62 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 image_ntsc.v(64) " "Warning: Verilog HDL assignment warning at image_ntsc.v(64): truncated value with size 32 to match size of target (11)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 64 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 image_ntsc.v(66) " "Warning: Verilog HDL assignment warning at image_ntsc.v(66): truncated value with size 32 to match size of target (11)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 image_ntsc.v(70) " "Warning: Verilog HDL assignment warning at image_ntsc.v(70): truncated value with size 32 to match size of target (1)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 70 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 image_ntsc.v(72) " "Warning: Verilog HDL assignment warning at image_ntsc.v(72): truncated value with size 32 to match size of target (1)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 72 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 image_ntsc.v(74) " "Warning: Verilog HDL assignment warning at image_ntsc.v(74): truncated value with size 32 to match size of target (1)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 74 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 image_ntsc.v(81) " "Warning: Verilog HDL assignment warning at image_ntsc.v(81): truncated value with size 32 to match size of target (9)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 81 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 image_ntsc.v(84) " "Warning: Verilog HDL assignment warning at image_ntsc.v(84): truncated value with size 32 to match size of target (9)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 image_ntsc.v(86) " "Warning: Verilog HDL assignment warning at image_ntsc.v(86): truncated value with size 32 to match size of target (9)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 86 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 image_ntsc.v(91) " "Warning: Verilog HDL assignment warning at image_ntsc.v(91): truncated value with size 32 to match size of target (1)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 91 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 image_ntsc.v(93) " "Warning: Verilog HDL assignment warning at image_ntsc.v(93): truncated value with size 32 to match size of target (1)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 93 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 image_ntsc.v(95) " "Warning: Verilog HDL assignment warning at image_ntsc.v(95): truncated value with size 32 to match size of target (1)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 95 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 image_ntsc.v(99) " "Warning: Verilog HDL assignment warning at image_ntsc.v(99): truncated value with size 32 to match size of target (1)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 99 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 image_ntsc.v(105) " "Warning: Verilog HDL assignment warning at image_ntsc.v(105): truncated value with size 32 to match size of target (8)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 105 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 image_ntsc.v(107) " "Warning: Verilog HDL assignment warning at image_ntsc.v(107): truncated value with size 32 to match size of target (8)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 107 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 image_ntsc.v(109) " "Warning: Verilog HDL assignment warning at image_ntsc.v(109): truncated value with size 32 to match size of target (8)" {  } { { "image_ntsc.v" "" { Text "D:/RedLogic/VBuffer/image_ntsc.v" 109 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "blank_gen mesure_card_top:inst5\|blank_gen:blank_gen0 " "Info: Elaborating entity \"blank_gen\" for hierarchy \"mesure_card_top:inst5\|blank_gen:blank_gen0\"" {  } { { "mesure_card_top.v" "blank_gen0" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 163 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "blank_rev_svga blank_gen.v(22) " "Info: (10035) Verilog HDL or VHDL information at blank_gen.v(22): object \"blank_rev_svga\" declared but not used" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(40) " "Warning: Verilog HDL assignment warning at blank_gen.v(40): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 40 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(42) " "Warning: Verilog HDL assignment warning at blank_gen.v(42): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 42 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(46) " "Warning: Verilog HDL assignment warning at blank_gen.v(46): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 46 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(49) " "Warning: Verilog HDL assignment warning at blank_gen.v(49): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(52) " "Warning: Verilog HDL assignment warning at blank_gen.v(52): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 52 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 blank_gen.v(56) " "Warning: Verilog HDL assignment warning at blank_gen.v(56): truncated value with size 32 to match size of target (8)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 56 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 blank_gen.v(59) " "Warning: Verilog HDL assignment warning at blank_gen.v(59): truncated value with size 32 to match size of target (8)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 blank_gen.v(62) " "Warning: Verilog HDL assignment warning at blank_gen.v(62): truncated value with size 32 to match size of target (8)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 62 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(66) " "Warning: Verilog HDL assignment warning at blank_gen.v(66): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(69) " "Warning: Verilog HDL assignment warning at blank_gen.v(69): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 69 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(72) " "Warning: Verilog HDL assignment warning at blank_gen.v(72): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 72 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(76) " "Warning: Verilog HDL assignment warning at blank_gen.v(76): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 76 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(78) " "Warning: Verilog HDL assignment warning at blank_gen.v(78): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(80) " "Warning: Verilog HDL assignment warning at blank_gen.v(80): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 80 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(84) " "Warning: Verilog HDL assignment warning at blank_gen.v(84): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(86) " "Warning: Verilog HDL assignment warning at blank_gen.v(86): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 86 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 blank_gen.v(88) " "Warning: Verilog HDL assignment warning at blank_gen.v(88): truncated value with size 32 to match size of target (1)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 88 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(92) " "Warning: Verilog HDL assignment warning at blank_gen.v(92): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 92 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(94) " "Warning: Verilog HDL assignment warning at blank_gen.v(94): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 94 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(96) " "Warning: Verilog HDL assignment warning at blank_gen.v(96): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 96 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(100) " "Warning: Verilog HDL assignment warning at blank_gen.v(100): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(102) " "Warning: Verilog HDL assignment warning at blank_gen.v(102): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 102 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 blank_gen.v(104) " "Warning: Verilog HDL assignment warning at blank_gen.v(104): truncated value with size 32 to match size of target (12)" {  } { { "blank_gen.v" "" { Text "D:/RedLogic/VBuffer/blank_gen.v" 104 0 0 } }  } 0}