i2c_altera.map.qmsg

视频采集

{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "P_WAIT 32'b00000000000000000000000000001010 " "Warning: Can't find a definition for parameter P_WAIT -- assuming 32'b00000000000000000000000000001010 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "IDLE 32'b00000000000000000000000000001011 " "Warning: Can't find a definition for parameter IDLE -- assuming 32'b00000000000000000000000000001011 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "I2C_W_OK 32'b00000000000000000000000000001100 " "Warning: Can't find a definition for parameter I2C_W_OK -- assuming 32'b00000000000000000000000000001100 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "HALT 32'b00000000000000000000000000001101 " "Warning: Can't find a definition for parameter HALT -- assuming 32'b00000000000000000000000000001101 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "CREATE_CHIP_RST 32'b00000000000000000000000000001110 " "Warning: Can't find a definition for parameter CREATE_CHIP_RST -- assuming 32'b00000000000000000000000000001110 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "odd_even_sig mesure_card_top inst5 " "Warning: Port \"odd_even_sig\" of type mesure_card_top and instance \"inst5\" is missing source signal" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 664 2368 2584 1176 "inst5" "" } } } }  } 0}
{ "Warning" "WGDFX_PIN_IGNORED" "ENC_HS " "Warning: Pin \"ENC_HS\" not connected" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 568 2592 2760 584 "ENC_HS" "" } } } }  } 0}
{ "Warning" "WGDFX_PIN_IGNORED" "ENC_VS " "Warning: Pin \"ENC_VS\" not connected" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 584 2592 2760 600 "ENC_VS" "" } } } }  } 0}
{ "Warning" "WGDFX_PIN_IGNORED" "mode_vga " "Warning: Pin \"mode_vga\" not connected" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 528 2320 2488 544 "mode_vga" "" } } } }  } 0}
{ "Warning" "WGDFX_PIN_IGNORED" "dsp_rst " "Warning: Pin \"dsp_rst\" not connected" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1072 2072 2240 1088 "dsp_rst" "" } } } }  } 0}
{ "Warning" "WGDFX_PIN_IGNORED" "pal_ntsc_flag " "Warning: Pin \"pal_ntsc_flag\" not connected" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1040 2072 2240 1056 "pal_ntsc_flag" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "PLL.v 1 1 " "Info: Using design file PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 PLL " "Info: Found entity 1: PLL" {  } { { "PLL.v" "" { Text "D:/RedLogic/VBuffer/PLL.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL PLL:inst3 " "Info: Elaborating entity \"PLL\" for hierarchy \"PLL:inst3\"" {  } { { "I2C_ALTERA.bdf" "inst3" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1472 496 752 1648 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll PLL:inst3\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"PLL:inst3\|altpll:altpll_component\"" {  } { { "PLL.v" "altpll_component" { Text "D:/RedLogic/VBuffer/PLL.v" 87 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesure_card_top mesure_card_top:inst5 " "Info: Elaborating entity \"mesure_card_top\" for hierarchy \"mesure_card_top:inst5\"" {  } { { "I2C_ALTERA.bdf" "inst5" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 664 2368 2584 1176 "inst5" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_fifo_wdb mesure_card_top.v(112) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(112): object \"s_fifo_wdb\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 112 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_fifo_wab mesure_card_top.v(113) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(113): object \"s_fifo_wab\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 113 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_fifo_wck mesure_card_top.v(114) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(114): object \"s_fifo_wck\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 114 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_fifo_wen mesure_card_top.v(115) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(115): object \"s_fifo_wen\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 115 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_fifo_rst mesure_card_top.v(120) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(120): object \"s_fifo_rst\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 120 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "test_pin mesure_card_top.v(122) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(122): object \"test_pin\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 122 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_fifo_rck mesure_card_top.v(124) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(124): object \"s_fifo_rck\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 124 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_fifo_ren mesure_card_top.v(125) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(125): object \"s_fifo_ren\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 125 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_fifo_rab mesure_card_top.v(126) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(126): object \"s_fifo_rab\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 126 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "data_valid mesure_card_top.v(127) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(127): object \"data_valid\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 127 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "qck_i mesure_card_top.v(135) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(135): object \"qck_i\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 135 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "blank_pal mesure_card_top.v(152) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(152): object \"blank_pal\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 152 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "r_req_dsp mesure_card_top.v(172) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(172): object \"r_req_dsp\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 172 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "r_ack_dsp mesure_card_top.v(174) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(174): object \"r_ack_dsp\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 174 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "pixel_vga mesure_card_top.v(336) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(336): object \"pixel_vga\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 336 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "pixel mesure_card_top.v(343) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(343): object \"pixel\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 343 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_ack_mask_vga mesure_card_top.v(372) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(372): object \"s_ack_mask_vga\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 372 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_ram_rdb_dsp mesure_card_top.v(420) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(420): object \"s_ram_rdb_dsp\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 420 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_ram_rab_dsp mesure_card_top.v(421) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(421): object \"s_ram_rab_dsp\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 421 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_ram_wen_dsp mesure_card_top.v(422) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(422): object \"s_ram_wen_dsp\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 422 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_ram_wdb_dsp mesure_card_top.v(430) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(430): object \"s_ram_wdb_dsp\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 430 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_ram_wab_dsp mesure_card_top.v(431) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(431): object \"s_ram_wab_dsp\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 431 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_req_dsp mesure_card_top.v(432) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(432): object \"s_req_dsp\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 432 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "mask_mode mesure_card_top.v(451) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(451): object \"mask_mode\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 451 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_ram_rdb_raw mesure_card_top.v(569) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(569): object \"s_ram_rdb_raw\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 569 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "s_ram_rab_wab mesure_card_top.v(570) " "Info: (10035) Verilog HDL or VHDL information at mesure_card_top.v(570): object \"s_ram_rab_wab\" declared but not used" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 570 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mesure_card_top.v(513) " "Warning: Verilog HDL assignment warning at mesure_card_top.v(513): truncated value with size 32 to match size of target (1)" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 513 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mesure_card_top.v(515) " "Warning: Verilog HDL assignment warning at mesure_card_top.v(515): truncated value with size 32 to match size of target (1)" {  } { { "mesure_card_top.v" "" { Text "D:/RedLogic/VBuffer/mesure_card_top.v" 515 0 0 } }  } 0}