decode_nga.tdf

视频采集

--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_DECODES=8 LPM_WIDTH=3 data enable eq
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 8 
SUBDESIGN decode_nga
( 
	data[2..0]	:	input;
	enable	:	input;
	eq[7..0]	:	output;
) 
VARIABLE 
	data_wire[2..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[7..0]	: WIRE;
	eq_wire[7..0]	: WIRE;
	w_anode3988w[3..0]	: WIRE;
	w_anode4005w[3..0]	: WIRE;
	w_anode4015w[3..0]	: WIRE;
	w_anode4025w[3..0]	: WIRE;
	w_anode4035w[3..0]	: WIRE;
	w_anode4045w[3..0]	: WIRE;
	w_anode4055w[3..0]	: WIRE;
	w_anode4065w[3..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	enable_wire = enable;
	eq[] = eq_node[];
	eq_node[7..0] = eq_wire[7..0];
	eq_wire[] = ( w_anode4065w[3..3], w_anode4055w[3..3], w_anode4045w[3..3], w_anode4035w[3..3], w_anode4025w[3..3], w_anode4015w[3..3], w_anode4005w[3..3], w_anode3988w[3..3]);
	w_anode3988w[] = ( (w_anode3988w[2..2] & (! data_wire[2..2])), (w_anode3988w[1..1] & (! data_wire[1..1])), (w_anode3988w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode4005w[] = ( (w_anode4005w[2..2] & (! data_wire[2..2])), (w_anode4005w[1..1] & (! data_wire[1..1])), (w_anode4005w[0..0] & data_wire[0..0]), enable_wire);
	w_anode4015w[] = ( (w_anode4015w[2..2] & (! data_wire[2..2])), (w_anode4015w[1..1] & data_wire[1..1]), (w_anode4015w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode4025w[] = ( (w_anode4025w[2..2] & (! data_wire[2..2])), (w_anode4025w[1..1] & data_wire[1..1]), (w_anode4025w[0..0] & data_wire[0..0]), enable_wire);
	w_anode4035w[] = ( (w_anode4035w[2..2] & data_wire[2..2]), (w_anode4035w[1..1] & (! data_wire[1..1])), (w_anode4035w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode4045w[] = ( (w_anode4045w[2..2] & data_wire[2..2]), (w_anode4045w[1..1] & (! data_wire[1..1])), (w_anode4045w[0..0] & data_wire[0..0]), enable_wire);
	w_anode4055w[] = ( (w_anode4055w[2..2] & data_wire[2..2]), (w_anode4055w[1..1] & data_wire[1..1]), (w_anode4055w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode4065w[] = ( (w_anode4065w[2..2] & data_wire[2..2]), (w_anode4065w[1..1] & data_wire[1..1]), (w_anode4065w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE