i2c_altera.tan.qmsg

视频采集

{ "Info" "ITAN_NO_REG2REG_EXIST" "P_VS " "Info: No valid register-to-register data paths exist for clock \"P_VS\"" {  } {  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "PLL:inst3\|altpll:altpll_component\|_clk0 register mesure_card_top:inst5\|datacnl:datacnl1\|w_ba\[1\] register mesure_card_top:inst5\|datacnl:datacnl1\|w_ba\[1\] 822 ps " "Info: Minimum slack time is 822 ps for clock \"PLL:inst3\|altpll:altpll_component\|_clk0\" between source register \"mesure_card_top:inst5\|datacnl:datacnl1\|w_ba\[1\]\" and destination register \"mesure_card_top:inst5\|datacnl:datacnl1\|w_ba\[1\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.613 ns + Shortest register register " "Info: + Shortest register to register delay is 0.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mesure_card_top:inst5\|datacnl:datacnl1\|w_ba\[1\] 1 REG LC_X18_Y10_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y10_N9; Fanout = 4; REG Node = 'mesure_card_top:inst5\|datacnl:datacnl1\|w_ba\[1\]'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { mesure_card_top:inst5|datacnl:datacnl1|w_ba[1] } "NODE_NAME" } "" } } { "datacnl.v" "" { Text "D:/RedLogic/VBuffer/datacnl.v" 98 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.613 ns) 0.613 ns mesure_card_top:inst5\|datacnl:datacnl1\|w_ba\[1\] 2 REG LC_X18_Y10_N9 4 " "Info: 2: + IC(0.000 ns) + CELL(0.613 ns) = 0.613 ns; Loc. = LC_X18_Y10_N9; Fanout = 4; REG Node = 'mesure_card_top:inst5\|datacnl:datacnl1\|w_ba\[1\]'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "0.613 ns" { mesure_card_top:inst5|datacnl:datacnl1|w_ba[1] mesure_card_top:inst5|datacnl:datacnl1|w_ba[1] } "NODE_NAME" } "" } } { "datacnl.v" "" { Text "D:/RedLogic/VBuffer/datacnl.v" 98 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_D