📄 i2c_altera.tan.qmsg

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💻 QMSG
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{ "Info" "ITDB_FULL_SLACK_RESULT" "SYSCLK register i2c_cmd:inst\|rom_addr\[3\] memory SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_eas:auto_generated\|ram_block1a7~porta_address_reg3 -5.758 ns " "Info: Slack time is -5.758 ns for clock \"SYSCLK\" between source register \"i2c_cmd:inst\|rom_addr\[3\]\" and destination memory \"SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_eas:auto_generated\|ram_block1a7~porta_address_reg3\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-3.949 ns + Largest register memory " "Info: + Largest register to memory requirement is -3.949 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "0.179 ns + " "Info: + Setup relationship between source and destination is 0.179 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 2.500 ns " "Info: + Latch edge is 2.500 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SYSCLK 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"SYSCLK\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 2.321 ns " "Info: - Launch edge is 2.321 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:inst3\|altpll:altpll_component\|_clk0 12.500 ns -5.179 ns  50 " "Info: Clock period of Source clock \"PLL:inst3\|altpll:altpll_component\|_clk0\" is 12.500 ns with  offset of -5.179 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.811 ns + Largest " "Info: + Largest clock skew is -3.811 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK destination 3.188 ns + Shortest memory " "Info: + Shortest clock path from clock \"SYSCLK\" to destination memory is 3.188 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYSCLK 1 CLK PIN_153 80 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 80; CLK Node = 'SYSCLK'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { SYSCLK } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1528 160 328 1544 "SYSCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.722 ns) 3.188 ns SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_eas:auto_generated\|ram_block1a7~porta_address_reg3 2 MEM M4K_X33_Y13 8 " "Info: 2: + IC(0.997 ns) + CELL(0.722 ns) = 3.188 ns; Loc. = M4K_X33_Y13; Fanout = 8; MEM Node = 'SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_eas:auto_generated\|ram_block1a7~porta_address_reg3'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "1.719 ns" { SYSCLK SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_eas.tdf" "" { Text "D:/RedLogic/VBuffer/db/altsyncram_eas.tdf" 174 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 68.73 % " "Info: Total cell delay = 2.191 ns ( 68.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns 31.27 % " "Info: Total interconnect delay = 0.997 ns ( 31.27 % )" {  } {  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.188 ns" { SYSCLK SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.188 ns" { SYSCLK SYSCLK~out0 SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } { 0.000ns 0.000ns 0.997ns } { 0.000ns 1.469ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst3\|altpll:altpll_component\|_clk0 source 6.999 ns - Longest register " "Info: - Longest clock path from clock \"PLL:inst3\|altpll:altpll_component\|_clk0\" to source register is 6.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_2 692 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 692; CLK Node = 'PLL:inst3\|altpll:altpll_component\|_clk0'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { PLL:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.779 ns) + CELL(0.935 ns) 2.714 ns clk_gen:inst19\|clkout 2 REG LC_X8_Y13_N9 148 " "Info: 2: + IC(1.779 ns) + CELL(0.935 ns) = 2.714 ns; Loc. = LC_X8_Y13_N9; Fanout = 148; REG Node = 'clk_gen:inst19\|clkout'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.714 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout } "NODE_NAME" } "" } } { "clk_gen.v" "" { Text "D:/RedLogic/VBuffer/clk_gen.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.574 ns) + CELL(0.711 ns) 6.999 ns i2c_cmd:inst\|rom_addr\[3\] 3 REG LC_X31_Y13_N9 6 " "Info: 3: + IC(3.574 ns) + CELL(0.711 ns) = 6.999 ns; Loc. = LC_X31_Y13_N9; Fanout = 6; REG Node = 'i2c_cmd:inst\|rom_addr\[3\]'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "4.285 ns" { clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[3] } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/RedLogic/VBuffer/i2c_cmd.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 23.52 % " "Info: Total cell delay = 1.646 ns ( 23.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.353 ns 76.48 % " "Info: Total interconnect delay = 5.353 ns ( 76.48 % )" {  } {  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[3] } { 0.000ns 1.779ns 3.574ns } { 0.000ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.188 ns" { SYSCLK SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.188 ns" { SYSCLK SYSCLK~out0 SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } { 0.000ns 0.000ns 0.997ns } { 0.000ns 1.469ns 0.722ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[3] } { 0.000ns 1.779ns 3.574ns } { 0.000ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "i2c_cmd.v" "" { Text "D:/RedLogic/VBuffer/i2c_cmd.v" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_eas.tdf" "" { Text "D:/RedLogic/VBuffer/db/altsyncram_eas.tdf" 174 2 0 } }  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.188 ns" { SYSCLK SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.188 ns" { SYSCLK SYSCLK~out0 SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } { 0.000ns 0.000ns 0.997ns } { 0.000ns 1.469ns 0.722ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[3] } { 0.000ns 1.779ns 3.574ns } { 0.000ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.809 ns - Longest register memory " "Info: - Longest register to memory delay is 1.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_cmd:inst\|rom_addr\[3\] 1 REG LC_X31_Y13_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y13_N9; Fanout = 6; REG Node = 'i2c_cmd:inst\|rom_addr\[3\]'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { i2c_cmd:inst|rom_addr[3] } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/RedLogic/VBuffer/i2c_cmd.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.426 ns) + CELL(0.383 ns) 1.809 ns SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_eas:auto_generated\|ram_block1a7~porta_address_reg3 2 MEM M4K_X33_Y13 8 " "Info: 2: + IC(1.426 ns) + CELL(0.383 ns) = 1.809 ns; Loc. = M4K_X33_Y13; Fanout = 8; MEM Node = 'SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_eas:auto_generated\|ram_block1a7~porta_address_reg3'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "1.809 ns" { i2c_cmd:inst|rom_addr[3] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_eas.tdf" "" { Text "D:/RedLogic/VBuffer/db/altsyncram_eas.tdf" 174 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns 21.17 % " "Info: Total cell delay = 0.383 ns ( 21.17 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.426 ns 78.83 % " "Info: Total interconnect delay = 1.426 ns ( 78.83 % )" {  } {  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "1.809 ns" { i2c_cmd:inst|rom_addr[3] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.809 ns" { i2c_cmd:inst|rom_addr[3] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } { 0.000ns 1.426ns } { 0.000ns 0.383ns } } }  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.188 ns" { SYSCLK SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.188 ns" { SYSCLK SYSCLK~out0 SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } { 0.000ns 0.000ns 0.997ns } { 0.000ns 1.469ns 0.722ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[3] } { 0.000ns 1.779ns 3.574ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "1.809 ns" { i2c_cmd:inst|rom_addr[3] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.809 ns" { i2c_cmd:inst|rom_addr[3] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3 } { 0.000ns 1.426ns } { 0.000ns 0.383ns } } }  } 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'SYSCLK' 14 " "Warning: Can't achieve timing requirement Clock Setup: 'SYSCLK' along 14 path(s). See Report window for details." {  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "PCLK register mesure_card_top:inst5\|receiver:receiver1\|r_ram_wab\[3\] register mesure_card_top:inst5\|receiver:receiver1\|r_req_video 127.63 MHz 7.835 ns Internal " "Info: Clock \"PCLK\" has Internal fmax of 127.63 MHz between source register \"mesure_card_top:inst5\|receiver:receiver1\|r_ram_wab\[3\]\" and destination register \"mesure_card_top:inst5\|receiver:receiver1\|r_req_video\" (period= 7.835 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.558 ns + Longest register register " "Info: + Longest register to register delay is 7.558 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mesure_card_top:inst5\|receiver:receiver1\|r_ram_wab\[3\] 1 REG LC_X32_Y18_N3 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y18_N3; Fanout = 6; REG Node = 'mesure_card_top:inst5\|receiver:receiver1\|r_ram_wab\[3\]'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] } "NODE_NAME" } "" } } { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 72 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.630 ns) + CELL(0.442 ns) 2.072 ns mesure_card_top:inst5\|receiver:receiver1\|r_ram_wab\[9\]~347 2 COMB LC_X32_Y19_N8 2 " "Info: 2: + IC(1.630 ns) + CELL(0.442 ns) = 2.072 ns; Loc. = LC_X32_Y19_N8; Fanout = 2; COMB Node = 'mesure_card_top:inst5\|receiver:receiver1\|r_ram_wab\[9\]~347'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.072 ns" { mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~347 } "NODE_NAME" } "" } } { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 72 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.203 ns) + CELL(0.442 ns) 3.717 ns mesure_card_top:inst5\|receiver:receiver1\|r_ram_wab\[9\]~350 3 COMB LC_X31_Y18_N3 1 " "Info: 3: + IC(1.203 ns) + CELL(0.442 ns) = 3.717 ns; Loc. = LC_X31_Y18_N3; Fanout = 1; COMB Node = 'mesure_card_top:inst5\|receiver:receiver1\|r_ram_wab\[9\]~350'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "1.645 ns" { mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~347 mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~350 } "NODE_NAME" } "" } } { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 72 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.103 ns) + CELL(0.738 ns) 7.558 ns mesure_card_top:inst5\|receiver:receiver1\|r_req_video 4 REG LC_X14_Y10_N6 2 " "Info: 4: + IC(3.103 ns) + CELL(0.738 ns) = 7.558 ns; Loc. = LC_X14_Y10_N6; Fanout = 2; REG Node = 'mesure_card_top:inst5\|receiver:receiver1\|r_req_video'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.841 ns" { mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~350 mesure_card_top:inst5|receiver:receiver1|r_req_video } "NODE_NAME" } "" } } { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 201 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 21.46 % " "Info: Total cell delay = 1.622 ns ( 21.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.936 ns 78.54 % " "Info: Total interconnect delay = 5.936 ns ( 78.54 % )" {  } {  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "7.558 ns" { mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~347 mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~350 mesure_card_top:inst5|receiver:receiver1|r_req_video } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.558 ns" { mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~347 mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~350 mesure_card_top:inst5|receiver:receiver1|r_req_video } { 0.000ns 1.630ns 1.203ns 3.103ns } { 0.000ns 0.442ns 0.442ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.016 ns - Smallest " "Info: - Smallest clock skew is -0.016 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PCLK destination 3.170 ns + Shortest register " "Info: + Shortest clock path from clock \"PCLK\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns PCLK 1 CLK PIN_28 274 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 274; CLK Node = 'PCLK'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { PCLK } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 816 1640 1808 832 "PCLK" "" } { 984 2912 2952 1000 "PCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns mesure_card_top:inst5\|receiver:receiver1\|r_req_video 2 REG LC_X14_Y10_N6 2 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X14_Y10_N6; Fanout = 2; REG Node = 'mesure_card_top:inst5\|receiver:receiver1\|r_req_video'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "1.701 ns" { PCLK mesure_card_top:inst5|receiver:receiver1|r_req_video } "NODE_NAME" } "" } } { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 201 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.77 % " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns 31.23 % " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.170 ns" { PCLK mesure_card_top:inst5|receiver:receiver1|r_req_video } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { PCLK PCLK~out0 mesure_card_top:inst5|receiver:receiver1|r_req_video } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PCLK source 3.186 ns - Longest register " "Info: - Longest clock path from clock \"PCLK\" to source register is 3.186 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns PCLK 1 CLK PIN_28 274 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 274; CLK Node = 'PCLK'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { PCLK } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 816 1640 1808 832 "PCLK" "" } { 984 2912 2952 1000 "PCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.711 ns) 3.186 ns mesure_card_top:inst5\|receiver:receiver1\|r_ram_wab\[3\] 2 REG LC_X32_Y18_N3 6 " "Info: 2: + IC(1.006 ns) + CELL(0.711 ns) = 3.186 ns; Loc. = LC_X32_Y18_N3; Fanout = 6; REG Node = 'mesure_card_top:inst5\|receiver:receiver1\|r_ram_wab\[3\]'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "1.717 ns" { PCLK mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] } "NODE_NAME" } "" } } { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 72 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.42 % " "Info: Total cell delay = 2.180 ns ( 68.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.006 ns 31.58 % " "Info: Total interconnect delay = 1.006 ns ( 31.58 % )" {  } {  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.186 ns" { PCLK mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.186 ns" { PCLK PCLK~out0 mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] } { 0.000ns 0.000ns 1.006ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.170 ns" { PCLK mesure_card_top:inst5|receiver:receiver1|r_req_video } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { PCLK PCLK~out0 mesure_card_top:inst5|receiver:receiver1|r_req_video } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.186 ns" { PCLK mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.186 ns" { PCLK PCLK~out0 mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] } { 0.000ns 0.000ns 1.006ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 72 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 201 -1 0 } }  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "7.558 ns" { mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~347 mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~350 mesure_card_top:inst5|receiver:receiver1|r_req_video } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.558 ns" { mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~347 mesure_card_top:inst5|receiver:receiver1|r_ram_wab[9]~350 mesure_card_top:inst5|receiver:receiver1|r_req_video } { 0.000ns 1.630ns 1.203ns 3.103ns } { 0.000ns 0.442ns 0.442ns 0.738ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.170 ns" { PCLK mesure_card_top:inst5|receiver:receiver1|r_req_video } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { PCLK PCLK~out0 mesure_card_top:inst5|receiver:receiver1|r_req_video } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.186 ns" { PCLK mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.186 ns" { PCLK PCLK~out0 mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3] } { 0.000ns 0.000ns 1.006ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
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