📄 i2c_altera.tan.qmsg
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{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "PLL:inst3\|altpll:altpll_component\|_clk0 register filter:inst8\|rst_out register i2c_cmd:inst\|rom_addr\[0\] 769 ps " "Info: Slack time is 769 ps for clock \"PLL:inst3\|altpll:altpll_component\|_clk0\" between source register \"filter:inst8\|rst_out\" and destination register \"i2c_cmd:inst\|rom_addr\[0\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.333 ns + Largest register register " "Info: + Largest register to register requirement is 4.333 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "2.321 ns + " "Info: + Setup relationship between source and destination is 2.321 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 2.321 ns " "Info: + Latch edge is 2.321 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL:inst3\|altpll:altpll_component\|_clk0 12.500 ns -5.179 ns 50 " "Info: Clock period of Destination clock \"PLL:inst3\|altpll:altpll_component\|_clk0\" is 12.500 ns with offset of -5.179 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source SYSCLK 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"SYSCLK\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.273 ns + Largest " "Info: + Largest clock skew is 2.273 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst3\|altpll:altpll_component\|_clk0 destination 6.999 ns + Shortest register " "Info: + Shortest clock path from clock \"PLL:inst3\|altpll:altpll_component\|_clk0\" to destination register is 6.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_2 692 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 692; CLK Node = 'PLL:inst3\|altpll:altpll_component\|_clk0'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { PLL:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.779 ns) + CELL(0.935 ns) 2.714 ns clk_gen:inst19\|clkout 2 REG LC_X8_Y13_N9 148 " "Info: 2: + IC(1.779 ns) + CELL(0.935 ns) = 2.714 ns; Loc. = LC_X8_Y13_N9; Fanout = 148; REG Node = 'clk_gen:inst19\|clkout'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.714 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout } "NODE_NAME" } "" } } { "clk_gen.v" "" { Text "D:/RedLogic/VBuffer/clk_gen.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.574 ns) + CELL(0.711 ns) 6.999 ns i2c_cmd:inst\|rom_addr\[0\] 3 REG LC_X35_Y13_N0 5 " "Info: 3: + IC(3.574 ns) + CELL(0.711 ns) = 6.999 ns; Loc. = LC_X35_Y13_N0; Fanout = 5; REG Node = 'i2c_cmd:inst\|rom_addr\[0\]'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "4.285 ns" { clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[0] } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/RedLogic/VBuffer/i2c_cmd.v" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 23.52 % " "Info: Total cell delay = 1.646 ns ( 23.52 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.353 ns 76.48 % " "Info: Total interconnect delay = 5.353 ns ( 76.48 % )" { } { } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[0] } { 0.000ns 1.779ns 3.574ns } { 0.000ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK source 4.726 ns - Longest register " "Info: - Longest clock path from clock \"SYSCLK\" to source register is 4.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYSCLK 1 CLK PIN_153 80 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 80; CLK Node = 'SYSCLK'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { SYSCLK } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1528 160 328 1544 "SYSCLK" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.035 ns) + CELL(0.935 ns) 3.439 ns filter:inst8\|cnt\[15\] 2 REG LC_X23_Y13_N7 2 " "Info: 2: + IC(1.035 ns) + CELL(0.935 ns) = 3.439 ns; Loc. = LC_X23_Y13_N7; Fanout = 2; REG Node = 'filter:inst8\|cnt\[15\]'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "1.970 ns" { SYSCLK filter:inst8|cnt[15] } "NODE_NAME" } "" } } { "filter.v" "" { Text "D:/RedLogic/VBuffer/filter.v" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.576 ns) + CELL(0.711 ns) 4.726 ns filter:inst8\|rst_out 3 REG LC_X23_Y13_N8 138 " "Info: 3: + IC(0.576 ns) + CELL(0.711 ns) = 4.726 ns; Loc. = LC_X23_Y13_N8; Fanout = 138; REG Node = 'filter:inst8\|rst_out'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "1.287 ns" { filter:inst8|cnt[15] filter:inst8|rst_out } "NODE_NAME" } "" } } { "filter.v" "" { Text "D:/RedLogic/VBuffer/filter.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 65.91 % " "Info: Total cell delay = 3.115 ns ( 65.91 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.611 ns 34.09 % " "Info: Total interconnect delay = 1.611 ns ( 34.09 % )" { } { } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "4.726 ns" { SYSCLK filter:inst8|cnt[15] filter:inst8|rst_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.726 ns" { SYSCLK SYSCLK~out0 filter:inst8|cnt[15] filter:inst8|rst_out } { 0.000ns 0.000ns 1.035ns 0.576ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[0] } { 0.000ns 1.779ns 3.574ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "4.726 ns" { SYSCLK filter:inst8|cnt[15] filter:inst8|rst_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.726 ns" { SYSCLK SYSCLK~out0 filter:inst8|cnt[15] filter:inst8|rst_out } { 0.000ns 0.000ns 1.035ns 0.576ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "filter.v" "" { Text "D:/RedLogic/VBuffer/filter.v" 3 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "i2c_cmd.v" "" { Text "D:/RedLogic/VBuffer/i2c_cmd.v" 10 -1 0 } } } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[0] } { 0.000ns 1.779ns 3.574ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "4.726 ns" { SYSCLK filter:inst8|cnt[15] filter:inst8|rst_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.726 ns" { SYSCLK SYSCLK~out0 filter:inst8|cnt[15] filter:inst8|rst_out } { 0.000ns 0.000ns 1.035ns 0.576ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.564 ns - Longest register register " "Info: - Longest register to register delay is 3.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns filter:inst8\|rst_out 1 REG LC_X23_Y13_N8 138 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y13_N8; Fanout = 138; REG Node = 'filter:inst8\|rst_out'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { filter:inst8|rst_out } "NODE_NAME" } "" } } { "filter.v" "" { Text "D:/RedLogic/VBuffer/filter.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.115 ns) + CELL(0.114 ns) 2.229 ns i2c_cmd:inst\|rom_addr\[6\]~165 2 COMB LC_X35_Y13_N2 2 " "Info: 2: + IC(2.115 ns) + CELL(0.114 ns) = 2.229 ns; Loc. = LC_X35_Y13_N2; Fanout = 2; COMB Node = 'i2c_cmd:inst\|rom_addr\[6\]~165'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.229 ns" { filter:inst8|rst_out i2c_cmd:inst|rom_addr[6]~165 } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/RedLogic/VBuffer/i2c_cmd.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.468 ns) + CELL(0.867 ns) 3.564 ns i2c_cmd:inst\|rom_addr\[0\] 3 REG LC_X35_Y13_N0 5 " "Info: 3: + IC(0.468 ns) + CELL(0.867 ns) = 3.564 ns; Loc. = LC_X35_Y13_N0; Fanout = 5; REG Node = 'i2c_cmd:inst\|rom_addr\[0\]'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "1.335 ns" { i2c_cmd:inst|rom_addr[6]~165 i2c_cmd:inst|rom_addr[0] } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/RedLogic/VBuffer/i2c_cmd.v" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.981 ns 27.53 % " "Info: Total cell delay = 0.981 ns ( 27.53 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.583 ns 72.47 % " "Info: Total interconnect delay = 2.583 ns ( 72.47 % )" { } { } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.564 ns" { filter:inst8|rst_out i2c_cmd:inst|rom_addr[6]~165 i2c_cmd:inst|rom_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.564 ns" { filter:inst8|rst_out i2c_cmd:inst|rom_addr[6]~165 i2c_cmd:inst|rom_addr[0] } { 0.000ns 2.115ns 0.468ns } { 0.000ns 0.114ns 0.867ns } } } } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.999 ns" { PLL:inst3|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[0] } { 0.000ns 1.779ns 3.574ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "4.726 ns" { SYSCLK filter:inst8|cnt[15] filter:inst8|rst_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.726 ns" { SYSCLK SYSCLK~out0 filter:inst8|cnt[15] filter:inst8|rst_out } { 0.000ns 0.000ns 1.035ns 0.576ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "3.564 ns" { filter:inst8|rst_out i2c_cmd:inst|rom_addr[6]~165 i2c_cmd:inst|rom_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.564 ns" { filter:inst8|rst_out i2c_cmd:inst|rom_addr[6]~165 i2c_cmd:inst|rom_addr[0] } { 0.000ns 2.115ns 0.468ns } { 0.000ns 0.114ns 0.867ns } } } } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "PLL:inst3\|altpll:altpll_component\|_clk1 memory mesure_card_top:inst5\|ram256_16to512_8:ram_s5\|altsyncram:altsyncram_component\|altsyncram_1751:auto_generated\|ram_block1a7~portb_address_reg8 memory mesure_card_top:inst5\|arbiter:arbiter0\|db_dsp_reg\[7\] 19.923 ns " "Info: Slack time is 19.923 ns for clock \"PLL:inst3\|altpll:altpll_component\|_clk1\" between source memory \"mesure_card_top:inst5\|ram256_16to512_8:ram_s5\|altsyncram:altsyncram_component\|altsyncram_1751:auto_generated\|ram_block1a7~portb_address_reg8\" and destination memory \"mesure_card_top:inst5\|arbiter:arbiter0\|db_dsp_reg\[7\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "196.97 MHz 5.077 ns " "Info: Fmax is 196.97 MHz (period= 5.077 ns)" { } { } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "24.242 ns + Largest memory memory " "Info: + Largest memory to memory requirement is 24.242 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "25.000 ns + " "Info: + Setup relationship between source and destination is 25.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 22.946 ns " "Info: + Latch edge is 22.946 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL:inst3\|altpll:altpll_component\|_clk1 25.000 ns -2.054 ns 50 " "Info: Clock period of Destination clock \"PLL:inst3\|altpll:altpll_component\|_clk1\" is 25.000 ns with offset of -2.054 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:inst3\|altpll:altpll_component\|_clk1 25.000 ns -2.054 ns 50 " "Info: Clock period of Source clock \"PLL:inst3\|altpll:altpll_component\|_clk1\" is 25.000 ns with offset of -2.054 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.015 ns + Largest " "Info: + Largest clock skew is -0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst3\|altpll:altpll_component\|_clk1 destination 2.381 ns + Shortest memory " "Info: + Shortest clock path from clock \"PLL:inst3\|altpll:altpll_component\|_clk1\" to destination memory is 2.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst3\|altpll:altpll_component\|_clk1 1 CLK PLL_2 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 33; CLK Node = 'PLL:inst3\|altpll:altpll_component\|_clk1'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { PLL:inst3|altpll:altpll_component|_clk1 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 760 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.678 ns) + CELL(0.703 ns) 2.381 ns mesure_card_top:inst5\|arbiter:arbiter0\|db_dsp_reg\[7\] 2 MEM M4K_X33_Y1 1 " "Info: 2: + IC(1.678 ns) + CELL(0.703 ns) = 2.381 ns; Loc. = M4K_X33_Y1; Fanout = 1; MEM Node = 'mesure_card_top:inst5\|arbiter:arbiter0\|db_dsp_reg\[7\]'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.381 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } "NODE_NAME" } "" } } { "arbiter.v" "" { Text "D:/RedLogic/VBuffer/arbiter.v" 118 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.703 ns 29.53 % " "Info: Total cell delay = 0.703 ns ( 29.53 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.678 ns 70.47 % " "Info: Total interconnect delay = 1.678 ns ( 70.47 % )" { } { } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.381 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.381 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } { 0.000ns 1.678ns } { 0.000ns 0.703ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst3\|altpll:altpll_component\|_clk1 source 2.396 ns - Longest memory " "Info: - Longest clock path from clock \"PLL:inst3\|altpll:altpll_component\|_clk1\" to source memory is 2.396 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst3\|altpll:altpll_component\|_clk1 1 CLK PLL_2 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 33; CLK Node = 'PLL:inst3\|altpll:altpll_component\|_clk1'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { PLL:inst3|altpll:altpll_component|_clk1 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 760 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.678 ns) + CELL(0.718 ns) 2.396 ns mesure_card_top:inst5\|ram256_16to512_8:ram_s5\|altsyncram:altsyncram_component\|altsyncram_1751:auto_generated\|ram_block1a7~portb_address_reg8 2 MEM M4K_X33_Y1 8 " "Info: 2: + IC(1.678 ns) + CELL(0.718 ns) = 2.396 ns; Loc. = M4K_X33_Y1; Fanout = 8; MEM Node = 'mesure_card_top:inst5\|ram256_16to512_8:ram_s5\|altsyncram:altsyncram_component\|altsyncram_1751:auto_generated\|ram_block1a7~portb_address_reg8'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.396 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 } "NODE_NAME" } "" } } { "db/altsyncram_1751.tdf" "" { Text "D:/RedLogic/VBuffer/db/altsyncram_1751.tdf" 269 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.718 ns 29.97 % " "Info: Total cell delay = 0.718 ns ( 29.97 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.678 ns 70.03 % " "Info: Total interconnect delay = 1.678 ns ( 70.03 % )" { } { } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.396 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.396 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 } { 0.000ns 1.678ns } { 0.000ns 0.718ns } } } } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.381 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.381 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } { 0.000ns 1.678ns } { 0.000ns 0.703ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.396 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.396 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 } { 0.000ns 1.678ns } { 0.000ns 0.718ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" { } { { "db/altsyncram_1751.tdf" "" { Text "D:/RedLogic/VBuffer/db/altsyncram_1751.tdf" 269 2 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" { } { { "arbiter.v" "" { Text "D:/RedLogic/VBuffer/arbiter.v" 118 -1 0 } } } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.381 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.381 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } { 0.000ns 1.678ns } { 0.000ns 0.703ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.396 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.396 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 } { 0.000ns 1.678ns } { 0.000ns 0.718ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns - Longest memory memory " "Info: - Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mesure_card_top:inst5\|ram256_16to512_8:ram_s5\|altsyncram:altsyncram_component\|altsyncram_1751:auto_generated\|ram_block1a7~portb_address_reg8 1 MEM M4K_X33_Y1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y1; Fanout = 8; MEM Node = 'mesure_card_top:inst5\|ram256_16to512_8:ram_s5\|altsyncram:altsyncram_component\|altsyncram_1751:auto_generated\|ram_block1a7~portb_address_reg8'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 } "NODE_NAME" } "" } } { "db/altsyncram_1751.tdf" "" { Text "D:/RedLogic/VBuffer/db/altsyncram_1751.tdf" 269 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns mesure_card_top:inst5\|arbiter:arbiter0\|db_dsp_reg\[7\] 2 MEM M4K_X33_Y1 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X33_Y1; Fanout = 1; MEM Node = 'mesure_card_top:inst5\|arbiter:arbiter0\|db_dsp_reg\[7\]'" { } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "4.319 ns" { mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } "NODE_NAME" } "" } } { "arbiter.v" "" { Text "D:/RedLogic/VBuffer/arbiter.v" 118 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" { } { } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "4.319 ns" { mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } } 0} } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.381 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.381 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } { 0.000ns 1.678ns } { 0.000ns 0.703ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "2.396 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.396 ns" { PLL:inst3|altpll:altpll_component|_clk1 mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 } { 0.000ns 1.678ns } { 0.000ns 0.718ns } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "4.319 ns" { mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } } 0}
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