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ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
params.v
1118759186
}
# hierarchies {
mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1
}
# end
# entity
ram256_32to1k_8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ram256_32to1k_8.v
1121931698
7
# storage
db|I2C_ALTERA.(18).cnf
db|I2C_ALTERA.(18).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|ram256_32to1k_8:ram_s0
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|I2C_ALTERA.(19).cnf
db|I2C_ALTERA.(19).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
10
PARAMETER_DEC
USR
NUMWORDS_B
1024
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_m951
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
clock0
clock1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component
}
# end
# entity
ram512_32
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ram512_32.v
1119367090
7
# storage
db|I2C_ALTERA.(21).cnf
db|I2C_ALTERA.(21).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|ram512_32:ram_s1
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|I2C_ALTERA.(22).cnf
db|I2C_ALTERA.(22).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
9
PARAMETER_DEC
USR
NUMWORDS_A
512
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
9
PARAMETER_DEC
USR
NUMWORDS_B
512
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_7851
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
clock0
clock1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
mesure_card_top:inst5|ram512_32:ram_s1|altsyncram:altsyncram_component
}
# end
# entity
sender_video
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sender_video.v
1143361866
7
# storage
db|I2C_ALTERA.(24).cnf
db|I2C_ALTERA.(24).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
DRAM_PIXEL
00000000000000000000000100000000
PARAMETER_BIN
DEF
IDLE
000001
PARAMETER_BIN
DEF
SEND1
000010
PARAMETER_BIN
DEF
SEND2
000100
PARAMETER_BIN
DEF
SEND3
001000
PARAMETER_BIN
DEF
SEND4
010000
PARAMETER_BIN
DEF
SEND5
100000
PARAMETER_BIN
DEF
}
# hierarchies {
mesure_card_top:inst5|sender_video:sender_video0
}
# end
# entity
sender_vga
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sender_vga.v
1122963628
7
# storage
db|I2C_ALTERA.(25).cnf
db|I2C_ALTERA.(25).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|sender_vga:sender_vga0
}
# end
# entity
rom_color_gen_RGB
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rom_color_gen_rgb.v
1122808472
7
# storage
db|I2C_ALTERA.(26).cnf
db|I2C_ALTERA.(26).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|sender_vga:sender_vga0|rom_color_gen_RGB:color_gen0
}
# end
# entity
rom1p164_Y
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rom1p164_y.v
1119348568
7
# storage
db|I2C_ALTERA.(27).cnf
db|I2C_ALTERA.(27).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|sender_vga:sender_vga0|rom1p164_Y:u0
mesure_card_top:inst5|sender_vga:sender_vga0|rom1p164_Y:u5
}
# end
# entity
rom1p596_Cr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rom1p596_cr.v
1119348634
7
# storage
db|I2C_ALTERA.(28).cnf
db|I2C_ALTERA.(28).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|sender_vga:sender_vga0|rom1p596_Cr:u1
}
# end
# entity
rom0p813_Cr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rom0p813_cr.v
1119347836
7
# storage
db|I2C_ALTERA.(29).cnf
db|I2C_ALTERA.(29).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|sender_vga:sender_vga0|rom0p813_Cr:u2
}
# end
# entity
rom0p392_Cb
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rom0p392_cb.v
1119347870
7
# storage
db|I2C_ALTERA.(30).cnf
db|I2C_ALTERA.(30).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|sender_vga:sender_vga0|rom0p392_Cb:u3
}
# end
# entity
rom2p017_Cb
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rom2p017_cb.v
1119348668
7
# storage
db|I2C_ALTERA.(31).cnf
db|I2C_ALTERA.(31).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|sender_vga:sender_vga0|rom2p017_Cb:u4
}
# end
# entity
vga_out
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
vga_out.v
1122802012
7
# storage
db|I2C_ALTERA.(32).cnf
db|I2C_ALTERA.(32).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|vga_out:vga_out0
}
# end
# entity
datacnl_dsp
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
datacnl_dsp.v
1126589060
7
# storage
db|I2C_ALTERA.(33).cnf
db|I2C_ALTERA.(33).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
IDLE
00000000000000000000001
PARAMETER_BIN
DEF
PRECHARGE
00000000000000000000010
PARAMETER_BIN
DEF
PRECHARGE_ACK
00000000000000000000100
PARAMETER_BIN
DEF
LOAD_MR
00000000000000000001000
PARAMETER_BIN
DEF
LOAD_MR_ACK
00000000000000000010000
PARAMETER_BIN
DEF
LOAD_R2
00000000000000000100000
PARAMETER_BIN
DEF
LOAD_R2_ACK
00000000000000001000000
PARAMETER_BIN
DEF
LOAD_R1
00000000000000010000000
PARAMETER_BIN
DEF
IDLE_WR
00000000000000100000000
PARAMETER_BIN
DEF
PAGE_WRITE
00000000000001000000000
PARAMETER_BIN
DEF
BURST_WRITE
00000000000010000000000
PARAMETER_BIN
DEF
BT_W
00000000000100000000000
PARAMETER_BIN
DEF
WAIT_ACK_W_T
00000000001000000000000
PARAMETER_BIN
DEF
PAGE_READ
00000000010000000000000
PARAMETER_BIN
DEF
BURST_READ
00000000100000000000000
PARAMETER_BIN
DEF
BT
00000001000000000000000
PARAMETER_BIN
DEF
LAST_DATA
00000010000000000000000
PARAMETER_BIN
DEF
CLOSE_PAGE_W
00000100000000000000000
PARAMETER_BIN
DEF
REFRESH_W
12345

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