i2c_altera.hif

视频采集

PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBIN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PLLENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKSWITCH
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ARESET
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PFDENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANACLR
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANREAD
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANWRITE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
clk
clk
clk
clk
clk
clk
inclk
inclk
locked
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|stratix_pll.inc
1107575584
c:|altera|quartus50|libraries|megafunctions|stratixii_pll.inc
1107575806
c:|altera|quartus50|libraries|megafunctions|cycloneii_pll.inc
1107575944
}
# end
# entity
image_NTSC
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
image_ntsc.v
1120190788
7
# storage
db|I2C_ALTERA.(4).cnf
db|I2C_ALTERA.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|image_NTSC:source
}
# end
# entity
ram1k_8to256_32
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ram1k_8to256_32.v
1118757880
7
# storage
db|I2C_ALTERA.(7).cnf
db|I2C_ALTERA.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|ram1k_8to256_32:ram_r0
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|I2C_ALTERA.(8).cnf
db|I2C_ALTERA.(8).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
8
PARAMETER_DEC
USR
NUMWORDS_B
256
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_l951
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
clock0
clock1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component
}
# end
# entity
ram512_8to256_16
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ram512_8to256_16.v
1118303276
7
# storage
db|I2C_ALTERA.(10).cnf
db|I2C_ALTERA.(10).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mesure_card_top:inst5|ram512_8to256_16:ram_r1
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|I2C_ALTERA.(11).cnf
db|I2C_ALTERA.(11).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
9
PARAMETER_DEC
USR
NUMWORDS_A
512
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
16
PARAMETER_DEC
USR
WIDTHAD_B
8
PARAMETER_DEC
USR
NUMWORDS_B
256
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_0751
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
clock0
clock1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
mesure_card_top:inst5|ram512_8to256_16:ram_r1|altsyncram:altsyncram_component
}
# end
# entity
datacnl
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
datacnl.v
1126441916
7
# storage
db|I2C_ALTERA.(13).cnf
db|I2C_ALTERA.(13).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
IDLE
000000000000000000001
PARAMETER_BIN
DEF
PRECHARGE
000000000000000000010
PARAMETER_BIN
DEF
PRECHARGE_ACK
000000000000000000100
PARAMETER_BIN
DEF
LOAD_MR
000000000000000001000
PARAMETER_BIN
DEF
LOAD_MR_ACK
000000000000000010000
PARAMETER_BIN
DEF
LOAD_R2
000000000000000100000
PARAMETER_BIN
DEF
LOAD_R2_ACK
000000000000001000000
PARAMETER_BIN
DEF
LOAD_R1
000000000000010000000
PARAMETER_BIN
DEF
IDLE_WR
000000000000100000000
PARAMETER_BIN
DEF
PAGE_WRITE
000000000001000000000
PARAMETER_BIN
DEF
BURST_WRITE
000000000010000000000
PARAMETER_BIN
DEF
BT_W
000000000100000000000
PARAMETER_BIN
DEF
WAIT_ACK_W_T
000000001000000000000
PARAMETER_BIN
DEF
PAGE_READ
000000010000000000000
PARAMETER_BIN
DEF
BURST_READ
000000100000000000000
PARAMETER_BIN
DEF
BT
000001000000000000000
PARAMETER_BIN
DEF
LAST_DATA
000010000000000000000
PARAMETER_BIN
DEF
CLOSE_PAGE_W
000100000000000000000
PARAMETER_BIN
DEF
REFRESH_W
001000000000000000000
PARAMETER_BIN
DEF
CLOSE_PAGE_R
010000000000000000000
PARAMETER_BIN
DEF
REFRESH_R
100000000000000000000
PARAMETER_BIN
DEF
RCD
00000000000000000000000000000011
PARAMETER_BIN
DEF
CL
00000000000000000000000000000011
PARAMETER_BIN
DEF
BL
00000000000000000000000010110100
PARAMETER_BIN
DEF
NOP
00000000000000000000000000000000
PARAMETER_BIN
DEF
READA
00000000000000000000000000000001
PARAMETER_BIN
DEF
WRITEA
00000000000000000000000000000010
PARAMETER_BIN
DEF
ARF
00000000000000000000000000000011
PARAMETER_BIN
DEF
PRECHRG
00000000000000000000000000000100
PARAMETER_BIN
DEF
LOAD_MODE
00000000000000000000000000000101
PARAMETER_BIN
DEF
LOAD_REG1
00000000000000000000000000000110
PARAMETER_BIN
DEF
LOAD_REG2
00000000000000000000000000000111
PARAMETER_BIN
DEF
}
# hierarchies {
mesure_card_top:inst5|datacnl:datacnl1
}
# end
# entity
sdr_sdram
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdr_sdram.v
1118761000
7
# storage
db|I2C_ALTERA.(14).cnf
db|I2C_ALTERA.(14).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
params.v
1118759186
}
# hierarchies {
mesure_card_top:inst5|sdr_sdram:sdr_sdram1
}
# end
# entity
control_interface
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
control_interface.v
1101628916
7
# storage
db|I2C_ALTERA.(15).cnf
db|I2C_ALTERA.(15).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
Params.v
1118759186
}
# hierarchies {
mesure_card_top:inst5|sdr_sdram:sdr_sdram1|control_interface:control1
}
# end
# entity
command
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
command.v
1119072676
7
# storage
db|I2C_ALTERA.(16).cnf
db|I2C_ALTERA.(16).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
params.v
1118759186
}
# hierarchies {
mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1
}
# end
# entity
sdr_data_path
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdr_data_path.v
1091448354
7
# storage
db|I2C_ALTERA.(17).cnf
db|I2C_ALTERA.(17).cnf
# internal_option {