i2c_altera.fit.qmsg

视频采集

{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 6 " "Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 6%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:14 " "Info: Fitter routing operations ending: elapsed time is 00:00:14" {  } {  } 0}
{ "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_MAIN_TITLE" "1 " "Info: Fitter merged 1 physical RAM blocks that contain multiple logical RAM slices into a single location" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_TITLE" "" "Info: Following physical RAM blocks contain multiple logical RAM slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X19_Y11 " "Info: Physical RAM block M4K_X19_Y11 contains the following RAM slices" { { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a7 " "Info: RAM slice \"ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a7\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a7 " "Info: RAM slice \"N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a7\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a6 " "Info: RAM slice \"N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a6\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a6 " "Info: RAM slice \"ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a6\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a5 " "Info: RAM slice \"N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a5\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a5 " "Info: RAM slice \"ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a5\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a4 " "Info: RAM slice \"ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a4\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a4 " "Info: RAM slice \"N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a4\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a3 " "Info: RAM slice \"ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a3\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a3 " "Info: RAM slice \"N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a3\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a2 " "Info: RAM slice \"N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a2\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a2 " "Info: RAM slice \"ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a2\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a1 " "Info: RAM slice \"ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a1\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a1 " "Info: RAM slice \"N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a1\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a0 " "Info: RAM slice \"N_REG:inst13\|altsyncram:altsyncram_component\|altsyncram_brs:auto_generated\|ram_block1a0\"" {  } {  } 2} { "Info" "IFYGR_FYGR_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a0 " "Info: RAM slice \"ENC_ROM:inst22\|altsyncram:altsyncram_component\|altsyncram_3mr:auto_generated\|ram_block1a0\"" {  } {  } 2}  } {  } 2}  } {  } 2}  } {  } 2}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "16 " "Warning: The following 16 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "db_dsp22\[15\] a permanently enabled " "Info: Pin db_dsp22\[15\] has a permanently enabled output enable" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1088 2632 2808 1104 "db_dsp22\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "db_dsp22\[15\]" } } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { db_dsp22[15] } "NODE_NAME" } "" } } { "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" { Floorplan "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" "" { db_dsp22[15] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "db_dsp22\[14\] a permanently enabled " "Info: Pin db_dsp22\[14\] has a permanently enabled output enable" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1088 2632 2808 1104 "db_dsp22\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "db_dsp22\[14\]" } } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { db_dsp22[14] } "NODE_NAME" } "" } } { "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" { Floorplan "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" "" { db_dsp22[14] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "db_dsp22\[13\] a permanently enabled " "Info: Pin db_dsp22\[13\] has a permanently enabled output enable" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1088 2632 2808 1104 "db_dsp22\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "db_dsp22\[13\]" } } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { db_dsp22[13] } "NODE_NAME" } "" } } { "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" { Floorplan "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" "" { db_dsp22[13] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "db_dsp22\[12\] a permanently enabled " "Info: Pin db_dsp22\[12\] has a permanently enabled output enable" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1088 2632 2808 1104 "db_dsp22\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "db_dsp22\[12\]" } } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { db_dsp22[12] } "NODE_NAME" } "" } } { "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" { Floorplan "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" "" { db_dsp22[12] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "db_dsp22\[11\] a permanently enabled " "Info: Pin db_dsp22\[11\] has a permanently enabled output enable" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1088 2632 2808 1104 "db_dsp22\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "db_dsp22\[11\]" } } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { db_dsp22[11] } "NODE_NAME" } "" } } { "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" { Floorplan "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" "" { db_dsp22[11] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "db_dsp22\[10\] a permanently enabled " "Info: Pin db_dsp22\[10\] has a permanently enabled output enable" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1088 2632 2808 1104 "db_dsp22\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "db_dsp22\[10\]" } } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { db_dsp22[10] } "NODE_NAME" } "" } } { "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" { Floorplan "D:/RedLogic/VBuffer/I2C_ALTERA.fld" "" "" { db_dsp22[10] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "db_dsp22\[9\] a permanently enabled " "Info: Pin db_dsp22\[9\] has a permanently enabled output enable" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1088 2632 2808 1104 "db_dsp22\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "db_dsp22\[9\]" } } } } { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" ""