i2c_altera.fit.eqn

视频采集

SB1_pixel_out[5]_PORT_A_data_in = BUS(CB1_s_ram_wdb[5], CB1_s_ram_wdb[3], CB1_s_ram_wdb[2], CB1_s_ram_wdb[0], CB1_s_ram_wdb[13], CB1_s_ram_wdb[11], CB1_s_ram_wdb[10], CB1_s_ram_wdb[8], CB1_s_ram_wdb[21], CB1_s_ram_wdb[19], CB1_s_ram_wdb[18], CB1_s_ram_wdb[16], CB1_s_ram_wdb[29], CB1_s_ram_wdb[27], CB1_s_ram_wdb[26], CB1_s_ram_wdb[24]);
SB1_pixel_out[5]_PORT_A_data_in_reg = DFFE(SB1_pixel_out[5]_PORT_A_data_in, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
SB1_pixel_out[5]_PORT_A_address_reg = DFFE(SB1_pixel_out[5]_PORT_A_address, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
SB1_pixel_out[5]_PORT_B_address_reg = DFFE(SB1_pixel_out[5]_PORT_B_address, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[5]_PORT_A_write_enable = VCC;
SB1_pixel_out[5]_PORT_A_write_enable_reg = DFFE(SB1_pixel_out[5]_PORT_A_write_enable, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_B_read_enable = VCC;
SB1_pixel_out[5]_PORT_B_read_enable_reg = DFFE(SB1_pixel_out[5]_PORT_B_read_enable, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[5]_clock_0 = GLOBAL(Z1__clk0);
SB1_pixel_out[5]_clock_1 = GLOBAL(PCLK);
SB1_pixel_out[5]_clock_enable_0 = CB1_s_enable;
SB1_pixel_out[5]_clock_enable_1 = VCC;
SB1_pixel_out[5]_PORT_B_data_out = MEMORY(SB1_pixel_out[5]_PORT_A_data_in_reg, , SB1_pixel_out[5]_PORT_A_address_reg, SB1_pixel_out[5]_PORT_B_address_reg, SB1_pixel_out[5]_PORT_A_write_enable_reg, SB1_pixel_out[5]_PORT_B_read_enable_reg, , , SB1_pixel_out[5]_clock_0, SB1_pixel_out[5]_clock_1, SB1_pixel_out[5]_clock_enable_0, SB1_pixel_out[5]_clock_enable_1, , );
SB1_pixel_out[5]_PORT_B_data_out_reg = DFFE(SB1_pixel_out[5]_PORT_B_data_out, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[2] = SB1_pixel_out[5]_PORT_B_data_out_reg[2];

--SB1_pixel_out[3] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[3] at M4K_X33_Y21
SB1_pixel_out[5]_PORT_A_data_in = BUS(CB1_s_ram_wdb[5], CB1_s_ram_wdb[3], CB1_s_ram_wdb[2], CB1_s_ram_wdb[0], CB1_s_ram_wdb[13], CB1_s_ram_wdb[11], CB1_s_ram_wdb[10], CB1_s_ram_wdb[8], CB1_s_ram_wdb[21], CB1_s_ram_wdb[19], CB1_s_ram_wdb[18], CB1_s_ram_wdb[16], CB1_s_ram_wdb[29], CB1_s_ram_wdb[27], CB1_s_ram_wdb[26], CB1_s_ram_wdb[24]);
SB1_pixel_out[5]_PORT_A_data_in_reg = DFFE(SB1_pixel_out[5]_PORT_A_data_in, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
SB1_pixel_out[5]_PORT_A_address_reg = DFFE(SB1_pixel_out[5]_PORT_A_address, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
SB1_pixel_out[5]_PORT_B_address_reg = DFFE(SB1_pixel_out[5]_PORT_B_address, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[5]_PORT_A_write_enable = VCC;
SB1_pixel_out[5]_PORT_A_write_enable_reg = DFFE(SB1_pixel_out[5]_PORT_A_write_enable, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_B_read_enable = VCC;
SB1_pixel_out[5]_PORT_B_read_enable_reg = DFFE(SB1_pixel_out[5]_PORT_B_read_enable, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[5]_clock_0 = GLOBAL(Z1__clk0);
SB1_pixel_out[5]_clock_1 = GLOBAL(PCLK);
SB1_pixel_out[5]_clock_enable_0 = CB1_s_enable;
SB1_pixel_out[5]_clock_enable_1 = VCC;
SB1_pixel_out[5]_PORT_B_data_out = MEMORY(SB1_pixel_out[5]_PORT_A_data_in_reg, , SB1_pixel_out[5]_PORT_A_address_reg, SB1_pixel_out[5]_PORT_B_address_reg, SB1_pixel_out[5]_PORT_A_write_enable_reg, SB1_pixel_out[5]_PORT_B_read_enable_reg, , , SB1_pixel_out[5]_clock_0, SB1_pixel_out[5]_clock_1, SB1_pixel_out[5]_clock_enable_0, SB1_pixel_out[5]_clock_enable_1, , );
SB1_pixel_out[5]_PORT_B_data_out_reg = DFFE(SB1_pixel_out[5]_PORT_B_data_out, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[3] = SB1_pixel_out[5]_PORT_B_data_out_reg[1];


--SB1_qd_reg_dly1[5] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[5] at LC_X28_Y18_N4
--operation mode is normal

SB1_qd_reg_dly1[5]_lut_out = H1L26Q & H1_qd_dly[5] # !H1L26Q & (H1L36Q & H1_qd_dly[5] # !H1L36Q & (H1_qd_dly1[5]));
SB1_qd_reg_dly1[5] = DFFEAS(SB1_qd_reg_dly1[5]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--SB1_qd_reg_dly1[4] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[4] at LC_X28_Y18_N3
--operation mode is normal

SB1_qd_reg_dly1[4]_lut_out = H1L36Q & H1_qd_dly[4] # !H1L36Q & (H1L26Q & H1_qd_dly[4] # !H1L26Q & (H1_qd_dly1[4]));
SB1_qd_reg_dly1[4] = DFFEAS(SB1_qd_reg_dly1[4]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--SB1_qd_reg_dly1[3] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[3] at LC_X28_Y18_N6
--operation mode is normal

SB1_qd_reg_dly1[3]_lut_out = H1L26Q & H1_qd_dly[3] # !H1L26Q & (H1L36Q & H1_qd_dly[3] # !H1L36Q & (H1_qd_dly1[3]));
SB1_qd_reg_dly1[3] = DFFEAS(SB1_qd_reg_dly1[3]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--SB1_qd_reg_dly1[2] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[2] at LC_X26_Y18_N2
--operation mode is normal

SB1_qd_reg_dly1[2]_lut_out = H1L26Q & H1_qd_dly[2] # !H1L26Q & (H1L36Q & H1_qd_dly[2] # !H1L36Q & (H1_qd_dly1[2]));
SB1_qd_reg_dly1[2] = DFFEAS(SB1_qd_reg_dly1[2]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--SB1_qd_reg_dly1[1] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[1] at LC_X28_Y18_N7
--operation mode is normal

SB1_qd_reg_dly1[1]_lut_out = H1L36Q & (H1_qd_dly[1]) # !H1L36Q & (H1L26Q & (H1_qd_dly[1]) # !H1L26Q & H1_qd_dly1[1]);
SB1_qd_reg_dly1[1] = DFFEAS(SB1_qd_reg_dly1[1]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--SB1_qd_reg_dly1[0] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[0] at LC_X28_Y18_N2
--operation mode is normal

SB1_qd_reg_dly1[0]_lut_out = H1L26Q & (H1_qd_dly[0]) # !H1L26Q & (H1L36Q & (H1_qd_dly[0]) # !H1L36Q & H1_qd_dly1[0]);
SB1_qd_reg_dly1[0] = DFFEAS(SB1_qd_reg_dly1[0]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--N1_dir is Led_run:inst21|dir at LC_X1_Y23_N8
--operation mode is normal

N1_dir_lut_out = N1_led[1] & (N1_dir # N1L86 & N1_led[2]) # !N1_led[1] & N1_dir & (N1_led[2] # !N1L86);
N1_dir = DFFEAS(N1_dir_lut_out, GLOBAL(N1_Mega_cnt[23]), GLOBAL(RST), , , , , , );


--N1_Mega_cnt[23] is Led_run:inst21|Mega_cnt[23] at LC_X8_Y13_N6
--operation mode is normal

N1_Mega_cnt[23]_carry_eqn = (!N1L26 & N1L46) # (N1L26 & N1L56);
N1_Mega_cnt[23]_lut_out = N1_Mega_cnt[23]_carry_eqn $ N1_Mega_cnt[23];
N1_Mega_cnt[23] = DFFEAS(N1_Mega_cnt[23]_lut_out, GLOBAL(SYSCLK), GLOBAL(RST), , , , , , );


--DC1_SA[10] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[10] at LC_X17_Y13_N0
--operation mode is normal

DC1_SA[10]_lut_out = DC1_do_rw & (!EC1_SC_PM) # !DC1_do_rw & (DC1_do_precharge & (!EC1_SC_PM) # !DC1_do_precharge & DC1L52);
DC1_SA[10] = DFFEAS(DC1_SA[10]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , !RST, );


--DC1_SA[9] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[9] at LC_X16_Y16_N3
--operation mode is normal

DC1_SA[9]_lut_out = RST & EC1_SADDR[17] & (DC1_do_reada # DC1_do_writea);
DC1_SA[9] = DFFEAS(DC1_SA[9]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--DC1_SA[8] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[8] at LC_X16_Y16_N9
--operation mode is normal

DC1_SA[8]_lut_out = RST & EC1_SADDR[16] & (DC1_do_reada # DC1_do_writea);
DC1_SA[8] = DFFEAS(DC1_SA[8]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--DC1_SA[7] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[7] at LC_X16_Y16_N0
--operation mode is normal

DC1_SA[7]_lut_out = DC1_do_writea & EC1_SADDR[15] # !DC1_do_writea & (DC1_do_reada & EC1_SADDR[15] # !DC1_do_reada & (EC1_SADDR[7]));
DC1_SA[7] = DFFEAS(DC1_SA[7]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , !RST, );


--DC1_SA[6] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[6] at LC_X15_Y15_N3
--operation mode is normal

DC1_SA[6]_lut_out = DC1_do_writea & (EC1_SADDR[14]) # !DC1_do_writea & (DC1_do_reada & (EC1_SADDR[14]) # !DC1_do_reada & EC1_SADDR[7]);
DC1_SA[6] = DFFEAS(DC1_SA[6]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , !RST, );


--DC1_SA[5] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[5] at LC_X14_Y14_N3
--operation mode is normal

DC1_SA[5]_lut_out = DC1_do_reada & EC1_SADDR[13] # !DC1_do_reada & (DC1_do_writea & EC1_SADDR[13] # !DC1_do_writea & (EC1_SADDR[5]));
DC1_SA[5] = DFFEAS(DC1_SA[5]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , !RST, );


--DC1_SA[4] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[4] at LC_X16_Y16_N6
--operation mode is normal

DC1_SA[4]_lut_out = DC1_do_writea & (EC1_SADDR[12]) # !DC1_do_writea & (DC1_do_reada & (EC1_SADDR[12]) # !DC1_do_reada & EC1_SADDR[4]);
DC1_SA[4] = DFFEAS(DC1_SA[4]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , !RST, );


--DC1_SA[3] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[3] at LC_X15_Y15_N0
--operation mode is normal

DC1_SA[3]_lut_out = DC1_do_writea & (EC1_SADDR[11]) # !DC1_do_writea & (DC1_do_reada & EC1_SADDR[11] # !DC1_do_reada & (EC1_SADDR[3]));
DC1_SA[3] = DFFEAS(DC1_SA[3]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , !RST, );


--DC1_SA[2] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[2] at LC_X14_Y14_N1
--operation mode is normal

DC1_SA[2]_lut_out = DC1_do_reada & EC1_SADDR[10] # !DC1_do_reada & (DC1_do_writea & EC1_SADDR[10] # !DC1_do_writea & (EC1_SADDR[5]));
DC1_SA[2] = DFFEAS(DC1_SA[2]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , !RST, );


--DC1_SA[1] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[1] at LC_X14_Y14_N6
--operation mode is normal

DC1_SA[1]_lut_out = DC1_do_reada & EC1_SADDR[9] # !DC1_do_reada & (DC1_do_writea & EC1_SADDR[9] # !DC1_do_writea & (EC1_SADDR[5]));
DC1_SA[1] = DFFEAS(DC1_SA[1]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , !RST, );


--DC1_SA[0] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[0] at LC_X15_Y15_N8
--operation mode is normal

DC1_SA[0]_lut_out = DC1_do_writea & EC1_SADDR[8] # !DC1_do_writea & (DC1_do_reada & EC1_SADDR[8] # !DC1_do_reada & (EC1_SADDR[0]));
DC1_SA[0] = DFFEAS(DC1_SA[0]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , !RST, );


--DC1_BA[1] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|BA[1] at LC_X18_Y16_N4
--operation mode is normal

DC1_BA[1]_lut_out = RST & (EC1_SADDR[20] & !DC1_do_load_mode);
DC1_BA[1] = DFFEAS(DC1_BA[1]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--DC1_BA[0] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|BA[0] at LC_X17_Y14_N4
--operation mode is normal

DC1_BA[0]_lut_out = EC1_SADDR[19] & RST & !DC1_do_load_mode;
DC1_BA[0] = DFFEAS(DC1_BA[0]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--DC1_do_precharge is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|do_precharge at LC_X17_Y13_N7
--operation mode is normal

DC1_do_precharge_lut_out = !DC1_do_precharge & (!DC1_command_done & EC1_PRECHARGE);
DC1_do_precharge = DFFEAS(DC1_do_precharge_lut_out, GLOBAL(Z1__clk0), GLOBAL(RST), , , , , , );


--DC1_do_reada is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|do_reada at LC_X16_Y13_N0
--operation mode is normal

DC1_do_reada_lut_out = DC1L13 & !EC1_timer_zero & EC1_READA & !DC1_do_reada;
DC1_do_reada = DFFEAS(DC1_do_reada_lut_out, GLOBAL(Z1__clk0), GLOBAL(RST), , , , , , );


--DC1L53 is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|always4~0 at LC_X17_Y15_N4
--operation mode is normal

DC1L53 = !DC1_do_reada & !DC1_do_writea;


--DC1_do_load_mode is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|do_load_mode at LC_X18_Y13_N8
--operation mode is normal

DC1_do_load_mode_lut_out = !DC1_do_load_mode & !DC1_command_done & EC1_LOAD_MODE;
DC1_do_load_mode = DFFEAS(DC1_do_load_mode_lut_out, GLOBAL(Z1__clk0), GLOBAL(RST), , , , , , );