i2c_altera.fit.eqn

视频采集

--SB1_pixel_out[4] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[4] at M4K_X33_Y20
SB1_pixel_out[7]_PORT_A_data_in = BUS(CB1_s_ram_wdb[7], CB1_s_ram_wdb[6], CB1_s_ram_wdb[4], CB1_s_ram_wdb[1], CB1_s_ram_wdb[15], CB1_s_ram_wdb[14], CB1_s_ram_wdb[12], CB1_s_ram_wdb[9], CB1_s_ram_wdb[23], CB1_s_ram_wdb[22], CB1_s_ram_wdb[20], CB1_s_ram_wdb[17], CB1_s_ram_wdb[31], CB1_s_ram_wdb[30], CB1_s_ram_wdb[28], CB1_s_ram_wdb[25]);
SB1_pixel_out[7]_PORT_A_data_in_reg = DFFE(SB1_pixel_out[7]_PORT_A_data_in, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
SB1_pixel_out[7]_PORT_A_address_reg = DFFE(SB1_pixel_out[7]_PORT_A_address, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
SB1_pixel_out[7]_PORT_B_address_reg = DFFE(SB1_pixel_out[7]_PORT_B_address, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[7]_PORT_A_write_enable = VCC;
SB1_pixel_out[7]_PORT_A_write_enable_reg = DFFE(SB1_pixel_out[7]_PORT_A_write_enable, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_B_read_enable = VCC;
SB1_pixel_out[7]_PORT_B_read_enable_reg = DFFE(SB1_pixel_out[7]_PORT_B_read_enable, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[7]_clock_0 = GLOBAL(Z1__clk0);
SB1_pixel_out[7]_clock_1 = GLOBAL(PCLK);
SB1_pixel_out[7]_clock_enable_0 = CB1_s_enable;
SB1_pixel_out[7]_clock_enable_1 = VCC;
SB1_pixel_out[7]_PORT_B_data_out = MEMORY(SB1_pixel_out[7]_PORT_A_data_in_reg, , SB1_pixel_out[7]_PORT_A_address_reg, SB1_pixel_out[7]_PORT_B_address_reg, SB1_pixel_out[7]_PORT_A_write_enable_reg, SB1_pixel_out[7]_PORT_B_read_enable_reg, , , SB1_pixel_out[7]_clock_0, SB1_pixel_out[7]_clock_1, SB1_pixel_out[7]_clock_enable_0, SB1_pixel_out[7]_clock_enable_1, , );
SB1_pixel_out[7]_PORT_B_data_out_reg = DFFE(SB1_pixel_out[7]_PORT_B_data_out, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[4] = SB1_pixel_out[7]_PORT_B_data_out_reg[2];

--SB1_pixel_out[6] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[6] at M4K_X33_Y20
SB1_pixel_out[7]_PORT_A_data_in = BUS(CB1_s_ram_wdb[7], CB1_s_ram_wdb[6], CB1_s_ram_wdb[4], CB1_s_ram_wdb[1], CB1_s_ram_wdb[15], CB1_s_ram_wdb[14], CB1_s_ram_wdb[12], CB1_s_ram_wdb[9], CB1_s_ram_wdb[23], CB1_s_ram_wdb[22], CB1_s_ram_wdb[20], CB1_s_ram_wdb[17], CB1_s_ram_wdb[31], CB1_s_ram_wdb[30], CB1_s_ram_wdb[28], CB1_s_ram_wdb[25]);
SB1_pixel_out[7]_PORT_A_data_in_reg = DFFE(SB1_pixel_out[7]_PORT_A_data_in, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
SB1_pixel_out[7]_PORT_A_address_reg = DFFE(SB1_pixel_out[7]_PORT_A_address, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
SB1_pixel_out[7]_PORT_B_address_reg = DFFE(SB1_pixel_out[7]_PORT_B_address, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[7]_PORT_A_write_enable = VCC;
SB1_pixel_out[7]_PORT_A_write_enable_reg = DFFE(SB1_pixel_out[7]_PORT_A_write_enable, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_B_read_enable = VCC;
SB1_pixel_out[7]_PORT_B_read_enable_reg = DFFE(SB1_pixel_out[7]_PORT_B_read_enable, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[7]_clock_0 = GLOBAL(Z1__clk0);
SB1_pixel_out[7]_clock_1 = GLOBAL(PCLK);
SB1_pixel_out[7]_clock_enable_0 = CB1_s_enable;
SB1_pixel_out[7]_clock_enable_1 = VCC;
SB1_pixel_out[7]_PORT_B_data_out = MEMORY(SB1_pixel_out[7]_PORT_A_data_in_reg, , SB1_pixel_out[7]_PORT_A_address_reg, SB1_pixel_out[7]_PORT_B_address_reg, SB1_pixel_out[7]_PORT_A_write_enable_reg, SB1_pixel_out[7]_PORT_B_read_enable_reg, , , SB1_pixel_out[7]_clock_0, SB1_pixel_out[7]_clock_1, SB1_pixel_out[7]_clock_enable_0, SB1_pixel_out[7]_clock_enable_1, , );
SB1_pixel_out[7]_PORT_B_data_out_reg = DFFE(SB1_pixel_out[7]_PORT_B_data_out, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[6] = SB1_pixel_out[7]_PORT_B_data_out_reg[1];


--SB1_qd_reg_dly1[7] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[7] at LC_X26_Y18_N4
--operation mode is normal

SB1_qd_reg_dly1[7]_lut_out = H1L26Q & (H1_qd_dly[7]) # !H1L26Q & (H1L36Q & (H1_qd_dly[7]) # !H1L36Q & H1_qd_dly1[7]);
SB1_qd_reg_dly1[7] = DFFEAS(SB1_qd_reg_dly1[7]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--UC1_safe_q[0] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[0] at LC_X35_Y16_N1
--operation mode is arithmetic

UC1_safe_q[0]_lut_out = !UC1_safe_q[0];
UC1_safe_q[0] = DFFEAS(UC1_safe_q[0]_lut_out, GLOBAL(PCLK), VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L4 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella0~COUT at LC_X35_Y16_N1
--operation mode is arithmetic

UC1L4_cout_0 = UC1_safe_q[0];
UC1L4 = CARRY(UC1L4_cout_0);

--UC1L5 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella0~COUTCOUT1_5 at LC_X35_Y16_N1
--operation mode is arithmetic

UC1L5_cout_1 = UC1_safe_q[0];
UC1L5 = CARRY(UC1L5_cout_1);


--UC1_safe_q[1] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[1] at LC_X35_Y16_N2
--operation mode is arithmetic

UC1_safe_q[1]_lut_out = UC1_safe_q[1] $ (UC1L4);
UC1_safe_q[1] = DFFEAS(UC1_safe_q[1]_lut_out, GLOBAL(PCLK), VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L7 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella1~COUT at LC_X35_Y16_N2
--operation mode is arithmetic

UC1L7_cout_0 = !UC1L4 # !UC1_safe_q[1];
UC1L7 = CARRY(UC1L7_cout_0);

--UC1L8 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella1~COUTCOUT1_4 at LC_X35_Y16_N2
--operation mode is arithmetic

UC1L8_cout_1 = !UC1L5 # !UC1_safe_q[1];
UC1L8 = CARRY(UC1L8_cout_1);


--UC1_safe_q[2] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[2] at LC_X35_Y16_N3
--operation mode is arithmetic

UC1_safe_q[2]_lut_out = UC1_safe_q[2] $ !UC1L7;
UC1_safe_q[2] = DFFEAS(UC1_safe_q[2]_lut_out, GLOBAL(PCLK), VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L01 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella2~COUT at LC_X35_Y16_N3
--operation mode is arithmetic

UC1L01_cout_0 = UC1_safe_q[2] & !UC1L7;
UC1L01 = CARRY(UC1L01_cout_0);

--UC1L11 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella2~COUTCOUT1_2 at LC_X35_Y16_N3
--operation mode is arithmetic

UC1L11_cout_1 = UC1_safe_q[2] & !UC1L8;
UC1L11 = CARRY(UC1L11_cout_1);


--UC1_safe_q[3] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[3] at LC_X35_Y16_N4
--operation mode is arithmetic

UC1_safe_q[3]_lut_out = UC1_safe_q[3] $ UC1L01;
UC1_safe_q[3] = DFFEAS(UC1_safe_q[3]_lut_out, GLOBAL(PCLK), VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L31 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella3~COUT at LC_X35_Y16_N4
--operation mode is arithmetic

UC1L31 = UC1L41;


--UC1_safe_q[4] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[4] at LC_X35_Y16_N5
--operation mode is arithmetic

UC1_safe_q[4]_carry_eqn = (!UC1L31 & GND) # (UC1L31 & VCC);
UC1_safe_q[4]_lut_out = UC1_safe_q[4] $ !UC1_safe_q[4]_carry_eqn;
UC1_safe_q[4] = DFFEAS(UC1_safe_q[4]_lut_out, GLOBAL(PCLK), VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L71 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella4~COUT at LC_X35_Y16_N5
--operation mode is arithmetic

UC1L71_cout_0 = UC1_safe_q[4] & !UC1L31;
UC1L71 = CARRY(UC1L71_cout_0);

--UC1L81 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella4~COUTCOUT1_4 at LC_X35_Y16_N5
--operation mode is arithmetic

UC1L81_cout_1 = UC1_safe_q[4] & !UC1L31;
UC1L81 = CARRY(UC1L81_cout_1);


--UC1_safe_q[5] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[5] at LC_X35_Y16_N6
--operation mode is arithmetic

UC1_safe_q[5]_carry_eqn = (!UC1L31 & UC1L71) # (UC1L31 & UC1L81);
UC1_safe_q[5]_lut_out = UC1_safe_q[5] $ (UC1_safe_q[5]_carry_eqn);
UC1_safe_q[5] = DFFEAS(UC1_safe_q[5]_lut_out, GLOBAL(PCLK), VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L02 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella5~COUT at LC_X35_Y16_N6
--operation mode is arithmetic

UC1L02_cout_0 = !UC1L71 # !UC1_safe_q[5];
UC1L02 = CARRY(UC1L02_cout_0);

--UC1L12 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella5~COUTCOUT1_4 at LC_X35_Y16_N6
--operation mode is arithmetic

UC1L12_cout_1 = !UC1L81 # !UC1_safe_q[5];
UC1L12 = CARRY(UC1L12_cout_1);


--SB1_blank_dly35 is mesure_card_top:inst5|sender_video:sender_video0|blank_dly35 at LC_X32_Y17_N5
--operation mode is normal

SB1_blank_dly35_lut_out = GND;
SB1_blank_dly35 = DFFEAS(SB1_blank_dly35_lut_out, GLOBAL(PCLK), VCC, , , SB1_blank_dly34, , , VCC);


--SB1_qd_reg_dly1[6] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[6] at LC_X26_Y18_N8
--operation mode is normal

SB1_qd_reg_dly1[6]_lut_out = H1L36Q & H1_qd_dly[6] # !H1L36Q & (H1L26Q & H1_qd_dly[6] # !H1L26Q & (H1_qd_dly1[6]));
SB1_qd_reg_dly1[6] = DFFEAS(SB1_qd_reg_dly1[6]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--SB1_pixel_out[5] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[5] at M4K_X33_Y21
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 256, Port A Width: 16, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
SB1_pixel_out[5]_PORT_A_data_in = BUS(CB1_s_ram_wdb[5], CB1_s_ram_wdb[3], CB1_s_ram_wdb[2], CB1_s_ram_wdb[0], CB1_s_ram_wdb[13], CB1_s_ram_wdb[11], CB1_s_ram_wdb[10], CB1_s_ram_wdb[8], CB1_s_ram_wdb[21], CB1_s_ram_wdb[19], CB1_s_ram_wdb[18], CB1_s_ram_wdb[16], CB1_s_ram_wdb[29], CB1_s_ram_wdb[27], CB1_s_ram_wdb[26], CB1_s_ram_wdb[24]);
SB1_pixel_out[5]_PORT_A_data_in_reg = DFFE(SB1_pixel_out[5]_PORT_A_data_in, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
SB1_pixel_out[5]_PORT_A_address_reg = DFFE(SB1_pixel_out[5]_PORT_A_address, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
SB1_pixel_out[5]_PORT_B_address_reg = DFFE(SB1_pixel_out[5]_PORT_B_address, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[5]_PORT_A_write_enable = VCC;
SB1_pixel_out[5]_PORT_A_write_enable_reg = DFFE(SB1_pixel_out[5]_PORT_A_write_enable, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_B_read_enable = VCC;
SB1_pixel_out[5]_PORT_B_read_enable_reg = DFFE(SB1_pixel_out[5]_PORT_B_read_enable, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[5]_clock_0 = GLOBAL(Z1__clk0);
SB1_pixel_out[5]_clock_1 = GLOBAL(PCLK);
SB1_pixel_out[5]_clock_enable_0 = CB1_s_enable;
SB1_pixel_out[5]_clock_enable_1 = VCC;
SB1_pixel_out[5]_PORT_B_data_out = MEMORY(SB1_pixel_out[5]_PORT_A_data_in_reg, , SB1_pixel_out[5]_PORT_A_address_reg, SB1_pixel_out[5]_PORT_B_address_reg, SB1_pixel_out[5]_PORT_A_write_enable_reg, SB1_pixel_out[5]_PORT_B_read_enable_reg, , , SB1_pixel_out[5]_clock_0, SB1_pixel_out[5]_clock_1, SB1_pixel_out[5]_clock_enable_0, SB1_pixel_out[5]_clock_enable_1, , );
SB1_pixel_out[5]_PORT_B_data_out_reg = DFFE(SB1_pixel_out[5]_PORT_B_data_out, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[5] = SB1_pixel_out[5]_PORT_B_data_out_reg[0];

--SB1_pixel_out[0] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[0] at M4K_X33_Y21
SB1_pixel_out[5]_PORT_A_data_in = BUS(CB1_s_ram_wdb[5], CB1_s_ram_wdb[3], CB1_s_ram_wdb[2], CB1_s_ram_wdb[0], CB1_s_ram_wdb[13], CB1_s_ram_wdb[11], CB1_s_ram_wdb[10], CB1_s_ram_wdb[8], CB1_s_ram_wdb[21], CB1_s_ram_wdb[19], CB1_s_ram_wdb[18], CB1_s_ram_wdb[16], CB1_s_ram_wdb[29], CB1_s_ram_wdb[27], CB1_s_ram_wdb[26], CB1_s_ram_wdb[24]);
SB1_pixel_out[5]_PORT_A_data_in_reg = DFFE(SB1_pixel_out[5]_PORT_A_data_in, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
SB1_pixel_out[5]_PORT_A_address_reg = DFFE(SB1_pixel_out[5]_PORT_A_address, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
SB1_pixel_out[5]_PORT_B_address_reg = DFFE(SB1_pixel_out[5]_PORT_B_address, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[5]_PORT_A_write_enable = VCC;
SB1_pixel_out[5]_PORT_A_write_enable_reg = DFFE(SB1_pixel_out[5]_PORT_A_write_enable, SB1_pixel_out[5]_clock_0, , , SB1_pixel_out[5]_clock_enable_0);
SB1_pixel_out[5]_PORT_B_read_enable = VCC;
SB1_pixel_out[5]_PORT_B_read_enable_reg = DFFE(SB1_pixel_out[5]_PORT_B_read_enable, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[5]_clock_0 = GLOBAL(Z1__clk0);
SB1_pixel_out[5]_clock_1 = GLOBAL(PCLK);
SB1_pixel_out[5]_clock_enable_0 = CB1_s_enable;
SB1_pixel_out[5]_clock_enable_1 = VCC;
SB1_pixel_out[5]_PORT_B_data_out = MEMORY(SB1_pixel_out[5]_PORT_A_data_in_reg, , SB1_pixel_out[5]_PORT_A_address_reg, SB1_pixel_out[5]_PORT_B_address_reg, SB1_pixel_out[5]_PORT_A_write_enable_reg, SB1_pixel_out[5]_PORT_B_read_enable_reg, , , SB1_pixel_out[5]_clock_0, SB1_pixel_out[5]_clock_1, SB1_pixel_out[5]_clock_enable_0, SB1_pixel_out[5]_clock_enable_1, , );
SB1_pixel_out[5]_PORT_B_data_out_reg = DFFE(SB1_pixel_out[5]_PORT_B_data_out, SB1_pixel_out[5]_clock_1, , , SB1_pixel_out[5]_clock_enable_1);
SB1_pixel_out[0] = SB1_pixel_out[5]_PORT_B_data_out_reg[3];

--SB1_pixel_out[2] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[2] at M4K_X33_Y21