i2c_altera.fit.eqn

视频采集

--operation mode is normal

SB1L24 = SB1_blank_dly36 & SB1_pixel_out[3] # !SB1_blank_dly36 & (TC1_q_b[4]);


--SB1L14 is mesure_card_top:inst5|sender_video:sender_video0|pixel[2]~69 at LC_X35_Y17_N8
--operation mode is normal

SB1L14 = SB1_blank_dly36 & SB1_pixel_out[2] # !SB1_blank_dly36 & (TC1_q_b[5]);


--SB1L04 is mesure_card_top:inst5|sender_video:sender_video0|pixel[1]~70 at LC_X35_Y17_N4
--operation mode is normal

SB1L04 = SB1_blank_dly36 & SB1_pixel_out[1] # !SB1_blank_dly36 & (TC1_q_b[6]);


--SB1L93 is mesure_card_top:inst5|sender_video:sender_video0|pixel[0]~71 at LC_X35_Y17_N7
--operation mode is normal

SB1L93 = SB1_blank_dly36 & SB1_pixel_out[0] # !SB1_blank_dly36 & (TC1_q_b[7]);


--N1_led[3] is Led_run:inst21|led[3] at LC_X1_Y23_N9
--operation mode is normal

N1_led[3]_lut_out = !N1_dir & N1_led[2];
N1_led[3] = DFFEAS(N1_led[3]_lut_out, GLOBAL(N1_Mega_cnt[23]), GLOBAL(RST), , , , , , );


--N1_led[2] is Led_run:inst21|led[2] at LC_X1_Y23_N3
--operation mode is normal

N1_led[2]_lut_out = N1_dir & N1_led[3] # !N1_dir & (!N1_led[1]);
N1_led[2] = DFFEAS(N1_led[2]_lut_out, GLOBAL(N1_Mega_cnt[23]), GLOBAL(RST), , , , , , );


--N1_led[1] is Led_run:inst21|led[1] at LC_X1_Y23_N6
--operation mode is normal

N1_led[1]_lut_out = N1_dir & (!N1_led[2]) # !N1_dir & !N1_led[0];
N1_led[1] = DFFEAS(N1_led[1]_lut_out, GLOBAL(N1_Mega_cnt[23]), GLOBAL(RST), , , , , , );


--N1_led[0] is Led_run:inst21|led[0] at LC_X1_Y23_N5
--operation mode is normal

N1_led[0]_lut_out = N1_dir & !N1_led[1];
N1_led[0] = DFFEAS(N1_led[0]_lut_out, GLOBAL(N1_Mega_cnt[23]), GLOBAL(RST), , , , , , );


--PB1_SA[10] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[10] at LC_X17_Y13_N3
--operation mode is normal

PB1_SA[10]_lut_out = DC1_SA[10];
PB1_SA[10] = DFFEAS(PB1_SA[10]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_SA[9] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[9] at LC_X16_Y16_N8
--operation mode is normal

PB1_SA[9]_lut_out = DC1_SA[9];
PB1_SA[9] = DFFEAS(PB1_SA[9]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_SA[8] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[8] at LC_X16_Y16_N7
--operation mode is normal

PB1_SA[8]_lut_out = DC1_SA[8];
PB1_SA[8] = DFFEAS(PB1_SA[8]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_SA[7] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[7] at LC_X16_Y16_N2
--operation mode is normal

PB1_SA[7]_lut_out = DC1_SA[7];
PB1_SA[7] = DFFEAS(PB1_SA[7]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_SA[6] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[6] at LC_X15_Y15_N4
--operation mode is normal

PB1_SA[6]_lut_out = DC1_SA[6];
PB1_SA[6] = DFFEAS(PB1_SA[6]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_SA[5] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[5] at LC_X14_Y14_N4
--operation mode is normal

PB1_SA[5]_lut_out = DC1_SA[5];
PB1_SA[5] = DFFEAS(PB1_SA[5]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_SA[4] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[4] at LC_X16_Y16_N4
--operation mode is normal

PB1_SA[4]_lut_out = DC1_SA[4];
PB1_SA[4] = DFFEAS(PB1_SA[4]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_SA[3] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[3] at LC_X15_Y15_N9
--operation mode is normal

PB1_SA[3]_lut_out = DC1_SA[3];
PB1_SA[3] = DFFEAS(PB1_SA[3]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_SA[2] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[2] at LC_X14_Y14_N8
--operation mode is normal

PB1_SA[2]_lut_out = DC1_SA[2];
PB1_SA[2] = DFFEAS(PB1_SA[2]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_SA[1] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[1] at LC_X14_Y14_N2
--operation mode is normal

PB1_SA[1]_lut_out = DC1_SA[1];
PB1_SA[1] = DFFEAS(PB1_SA[1]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_SA[0] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[0] at LC_X15_Y15_N2
--operation mode is normal

PB1_SA[0]_lut_out = DC1_SA[0];
PB1_SA[0] = DFFEAS(PB1_SA[0]_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_BA[1] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|BA[1] at LC_X18_Y16_N2
--operation mode is normal

PB1_BA[1]_lut_out = GND;
PB1_BA[1] = DFFEAS(PB1_BA[1]_lut_out, GLOBAL(Z1__clk0), VCC, , , DC1_BA[1], , , VCC);


--PB1_BA[0] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|BA[0] at LC_X17_Y14_N2
--operation mode is normal

PB1_BA[0]_lut_out = GND;
PB1_BA[0] = DFFEAS(PB1_BA[0]_lut_out, GLOBAL(Z1__clk0), VCC, , , DC1_BA[0], , , VCC);


--DC1_CAS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|CAS_N at LC_X18_Y15_N0
--operation mode is normal

DC1_CAS_N_lut_out = !DC1_do_refresh & (DC1L63 # DC1L5);
DC1_CAS_N = DFFEAS(DC1_CAS_N_lut_out, GLOBAL(Z1__clk0), VCC, , , VCC, , , !RST);


--DC1_CS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|CS_N at LC_X35_Y18_N9
--operation mode is normal

DC1_CS_N_lut_out = !RST;
DC1_CS_N = DFFEAS(DC1_CS_N_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--DC1_RAS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|RAS_N at LC_X18_Y15_N6
--operation mode is normal

DC1_RAS_N_lut_out = !DC1_do_refresh & (DC1L63 # !DC1L11);
DC1_RAS_N = DFFEAS(DC1_RAS_N_lut_out, GLOBAL(Z1__clk0), VCC, , , VCC, , , !RST);


--DC1_WE_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|WE_N at LC_X18_Y15_N5
--operation mode is normal

DC1_WE_N_lut_out = DC1_do_refresh # !DC1L63 & (DC1L82);
DC1_WE_N = DFFEAS(DC1_WE_N_lut_out, GLOBAL(Z1__clk0), VCC, , , VCC, , , !RST);


--SB1_pixel_out[7] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[7] at M4K_X33_Y20
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 256, Port A Width: 16, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
SB1_pixel_out[7]_PORT_A_data_in = BUS(CB1_s_ram_wdb[7], CB1_s_ram_wdb[6], CB1_s_ram_wdb[4], CB1_s_ram_wdb[1], CB1_s_ram_wdb[15], CB1_s_ram_wdb[14], CB1_s_ram_wdb[12], CB1_s_ram_wdb[9], CB1_s_ram_wdb[23], CB1_s_ram_wdb[22], CB1_s_ram_wdb[20], CB1_s_ram_wdb[17], CB1_s_ram_wdb[31], CB1_s_ram_wdb[30], CB1_s_ram_wdb[28], CB1_s_ram_wdb[25]);
SB1_pixel_out[7]_PORT_A_data_in_reg = DFFE(SB1_pixel_out[7]_PORT_A_data_in, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
SB1_pixel_out[7]_PORT_A_address_reg = DFFE(SB1_pixel_out[7]_PORT_A_address, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
SB1_pixel_out[7]_PORT_B_address_reg = DFFE(SB1_pixel_out[7]_PORT_B_address, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[7]_PORT_A_write_enable = VCC;
SB1_pixel_out[7]_PORT_A_write_enable_reg = DFFE(SB1_pixel_out[7]_PORT_A_write_enable, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_B_read_enable = VCC;
SB1_pixel_out[7]_PORT_B_read_enable_reg = DFFE(SB1_pixel_out[7]_PORT_B_read_enable, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[7]_clock_0 = GLOBAL(Z1__clk0);
SB1_pixel_out[7]_clock_1 = GLOBAL(PCLK);
SB1_pixel_out[7]_clock_enable_0 = CB1_s_enable;
SB1_pixel_out[7]_clock_enable_1 = VCC;
SB1_pixel_out[7]_PORT_B_data_out = MEMORY(SB1_pixel_out[7]_PORT_A_data_in_reg, , SB1_pixel_out[7]_PORT_A_address_reg, SB1_pixel_out[7]_PORT_B_address_reg, SB1_pixel_out[7]_PORT_A_write_enable_reg, SB1_pixel_out[7]_PORT_B_read_enable_reg, , , SB1_pixel_out[7]_clock_0, SB1_pixel_out[7]_clock_1, SB1_pixel_out[7]_clock_enable_0, SB1_pixel_out[7]_clock_enable_1, , );
SB1_pixel_out[7]_PORT_B_data_out_reg = DFFE(SB1_pixel_out[7]_PORT_B_data_out, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[7] = SB1_pixel_out[7]_PORT_B_data_out_reg[0];

--SB1_pixel_out[1] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[1] at M4K_X33_Y20
SB1_pixel_out[7]_PORT_A_data_in = BUS(CB1_s_ram_wdb[7], CB1_s_ram_wdb[6], CB1_s_ram_wdb[4], CB1_s_ram_wdb[1], CB1_s_ram_wdb[15], CB1_s_ram_wdb[14], CB1_s_ram_wdb[12], CB1_s_ram_wdb[9], CB1_s_ram_wdb[23], CB1_s_ram_wdb[22], CB1_s_ram_wdb[20], CB1_s_ram_wdb[17], CB1_s_ram_wdb[31], CB1_s_ram_wdb[30], CB1_s_ram_wdb[28], CB1_s_ram_wdb[25]);
SB1_pixel_out[7]_PORT_A_data_in_reg = DFFE(SB1_pixel_out[7]_PORT_A_data_in, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
SB1_pixel_out[7]_PORT_A_address_reg = DFFE(SB1_pixel_out[7]_PORT_A_address, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
SB1_pixel_out[7]_PORT_B_address_reg = DFFE(SB1_pixel_out[7]_PORT_B_address, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[7]_PORT_A_write_enable = VCC;
SB1_pixel_out[7]_PORT_A_write_enable_reg = DFFE(SB1_pixel_out[7]_PORT_A_write_enable, SB1_pixel_out[7]_clock_0, , , SB1_pixel_out[7]_clock_enable_0);
SB1_pixel_out[7]_PORT_B_read_enable = VCC;
SB1_pixel_out[7]_PORT_B_read_enable_reg = DFFE(SB1_pixel_out[7]_PORT_B_read_enable, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[7]_clock_0 = GLOBAL(Z1__clk0);
SB1_pixel_out[7]_clock_1 = GLOBAL(PCLK);
SB1_pixel_out[7]_clock_enable_0 = CB1_s_enable;
SB1_pixel_out[7]_clock_enable_1 = VCC;
SB1_pixel_out[7]_PORT_B_data_out = MEMORY(SB1_pixel_out[7]_PORT_A_data_in_reg, , SB1_pixel_out[7]_PORT_A_address_reg, SB1_pixel_out[7]_PORT_B_address_reg, SB1_pixel_out[7]_PORT_A_write_enable_reg, SB1_pixel_out[7]_PORT_B_read_enable_reg, , , SB1_pixel_out[7]_clock_0, SB1_pixel_out[7]_clock_1, SB1_pixel_out[7]_clock_enable_0, SB1_pixel_out[7]_clock_enable_1, , );
SB1_pixel_out[7]_PORT_B_data_out_reg = DFFE(SB1_pixel_out[7]_PORT_B_data_out, SB1_pixel_out[7]_clock_1, , , SB1_pixel_out[7]_clock_enable_1);
SB1_pixel_out[1] = SB1_pixel_out[7]_PORT_B_data_out_reg[3];