receiver.v

视频采集

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/* Title          :	virtual image source                          */
/* Project        :	virtual source                                */
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// File name      :  receiver.v 
// Purpose        :    
// Author<email>  :  [e-mail]
// Created On     :  2003/09/27
// Last update    :	 2003/09/27 
// Platform :     :	 Windows2000 
// Simulators     :	 MaxplussII 10.1 
// Synthesizers   :	 MaxplussII 10.1 
// Targets Device :	 (MAX7000AE)EPM7128AETC100-10 
// Comments       :  -
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/* Revision History :											   */
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module receiver(
	rst,	
	H_sig,
	V_sig,
	odd_even_sig,
	qd,
	clk,
	qfv,
	
	r_ram_wdb,
	r_ram_wab,
	r_ram_wab_raw,
	r_ram_wdb_test,
		
	r_req,
	r_ack_video,
	r_busy,
	
	r_req_dsp,
	r_ack_dsp,
	
	start_read,
	mode_vga,
	ODD_STATE
	);					
/*** ports ***/
input	rst;
input	[7:0]	qd;
input	clk,qfv,H_sig,V_sig,odd_even_sig;
input	r_ack_video,r_ack_dsp;

output	[7:0]	r_ram_wdb,r_ram_wdb_test;
output	r_req,r_req_dsp;
output	[9:0]	r_ram_wab;
output	[8:0]	r_ram_wab_raw;
output	start_read;
output	r_busy;
input	mode_vga;
output	[2:0]	ODD_STATE;
/***reg***/
wire	[7:0]	r_ram_wdb;
reg	r_req_dsp ;
reg	[9:0]	r_ram_wab;
reg	start_read;
//internal 
reg	[2:0]	STATE,next;
reg	qfv_reg,h_reg,v_reg ;
reg	[7:0]	qd_reg;
reg	odd_even_reg,v_reg1;

always @ (posedge clk) begin	
	h_reg   <= H_sig;
	v_reg   <= V_sig;
	v_reg1  <= v_reg;
	qd_reg  <= qd;
	odd_even_reg <= odd_even_sig;
	qfv_reg <= qfv ;
	end
	
reg	[1:0]	ODD_STATE;
reg	odd_start;
always @ (posedge clk or negedge rst)
if(!rst) begin
	ODD_STATE <= 0;
	odd_start <= 0;
	end
else 
	case(ODD_STATE)
/*	'd5:	if(qfv_reg)
				ODD_STATE <= 3'd0;
			else
				ODD_STATE <= 3'd5;*/
	'd0:	if(qd_reg==8'hff)
				ODD_STATE <= 3'd1;
			else
				ODD_STATE <= 3'd0;
	'd1:	if(qd_reg==8'h00)
				ODD_STATE <= 3'd2;
			else
				ODD_STATE <= 3'd0;
	'd2:	if(qd_reg==8'h00)
				ODD_STATE <= 3'd3;
			else
				ODD_STATE <= 3'd0;
	'd3:	if(qd_reg==8'hc7)	begin  // B6
				ODD_STATE <= 3'd0;
				odd_start <= 1'b1;
				end
			else if(qd_reg==8'h80) begin
				ODD_STATE <= 3'd0;
				odd_start <= 1'b0;
				end
			else 
				ODD_STATE <= 3'd0;
	endcase	
	
always @ (posedge clk or negedge rst)
if(!rst)
	start_read <= 0;
else if(STATE=='d2)
	start_read <= 1;
	
always @ (posedge  clk or negedge rst)
if(!rst)
	STATE <= 'd0;
else
	STATE <= next;
     
always @ (STATE or qfv_reg or v_reg or v_reg1 or odd_start)
begin
    case(STATE)
    'd0: if(v_reg & !v_reg1 & odd_start)	next = 'd1;////& odd_even_reg)
         else		next = 'd0;
    'd1: if(v_reg)	next = 'd2;
         else		next = 'd1;
    'd2: if(qfv_reg)	next = 'd3;
         else		next = 'd2;
    'd3: if(!qfv_reg)	next = 'd4;
         else		next = 'd3;
    'd4: if(!v_reg)	next = 'd1;
         else if(qfv_reg)	next = 'd3;
         else		next = 'd4;
    default:		next = 'd0;
    endcase
end
                                                      
always @ (posedge  clk or negedge rst)
if(!rst)
	r_ram_wab <= 'd0;
else if(qfv_reg && (STATE!=1'b0)) begin
	if(r_ram_wab == 'd719)
		r_ram_wab <= 0;
	else
		r_ram_wab <= r_ram_wab + 1;
	end
else
	r_ram_wab <= 0;

reg	[8:0]	r_ram_wab_raw;	
always @ (posedge  clk or negedge rst)
if(!rst)
	r_ram_wab_raw <= 'd0;
else if(qfv_reg && (STATE!=1'b0)) begin
	if(r_ram_wab_raw == 'd359)
		r_ram_wab_raw <= 0;
	else
		r_ram_wab_raw <= r_ram_wab_raw + 1;
	end
else
	r_ram_wab_raw <= 0;

assign	r_ram_wdb = qd_reg;

reg	[7:0]	r_ram_wdb_test;
always @ (posedge clk or negedge rst)
if(!rst)
	r_ram_wdb_test <= 0;
else if(qfv_reg)
	r_ram_wdb_test <= r_ram_wdb_test + 1;
else //if(!v_reg)
	r_ram_wdb_test <= 0;

reg	r_req_video;
always @ (posedge clk or negedge rst)
if(!rst)
    r_req_video <= 0;
else if(r_ram_wab=='d671 ) //'d658
    r_req_video <= 1;
else if(r_ack_video)
    r_req_video <= 0;

reg	r_busy_video;
always @ (posedge clk or negedge rst)
if(!rst)
    r_busy_video <= 0;
else if(r_ram_wab>='d678 )//'d560
    r_busy_video <= 0;
else// if(r_ack_video)
    r_busy_video <= 0;


always @ (posedge clk or negedge rst)
if(!rst)
    r_req_dsp <= 0;
else if(r_ram_wab_raw=='d320) //'d320
    r_req_dsp <= 1;
else// if(r_ack_dsp)
    r_req_dsp <= 0;

reg	r_req_vga;
always @ (posedge clk or negedge rst)
if(!rst)
    r_req_vga <= 0;
else if(r_ram_wab=='d680 )
    r_req_vga <= 1;
else if(r_ack_video)
    r_req_vga <= 0;

reg	r_busy_vga;
always @ (posedge clk or negedge rst)
if(!rst)
    r_busy_vga <= 0;
else if(r_ram_wab>='d580 )
    r_busy_vga <= 1;
else// if(r_ack_video)
    r_busy_vga <= 0;

wire	r_req = mode_vga?r_req_vga:r_req_video;
wire	r_busy = mode_vga?r_busy_vga:r_busy_video;
endmodule