i2c_altera.map.rpt

视频采集

; Top-level Entity Name       ; I2C_ALTERA                                    ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; 1,321                                         ;
; Total pins                  ; 132                                           ;
; Total virtual pins          ; 0                                             ;
; Total memory bits           ; 27,912                                        ;
; Total PLLs                  ; 1                                             ;
+-----------------------------+-----------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C12Q240C8 ;               ;
; Top-level entity name                                              ; I2C_ALTERA   ; I2C_ALTERA    ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Use smart compilation                                              ; On           ; Off           ;
; Type of Retiming Performed During Resynthesis                      ; Full         ;               ;
; Resynthesis Optimization Effort                                    ; Normal       ;               ;
; Physical Synthesis Level for Resynthesis                           ; Normal       ;               ;
; Use Generated Physical Constraints File                            ; On           ;               ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; Add Pass-Through Logic to Inferred RAMs                            ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;
; Ignore SOFT Buffers                                                ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off          ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced     ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70           ; 70            ;
; Auto Carry Chains                                                  ; On           ; On            ;
; Auto Open-Drain Pins                                               ; On           ; On            ;
; Remove Duplicate Logic                                             ; On           ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off          ; Off           ;
; Perform gate-level register retiming                               ; Off          ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On           ; On            ;
; Auto ROM Replacement                                               ; On           ; On            ;
; Auto RAM Replacement                                               ; On           ; On            ;
; Auto Shift Register Replacement                                    ; On           ; On            ;
; Auto Clock Enable Replacement                                      ; On           ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On           ; On            ;
; Auto RAM Block Balancing                                           ; On           ; On            ;
; Auto Resource Sharing                                              ; Off          ; Off           ;
; Allow Any RAM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any ROM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any Shift Register Size For Recognition                      ; Off          ; Off           ;
; Enable M512 Memory Blocks                                          ; On           ; On            ;
; Maximum Number of M512 Memory Blocks                               ; -1           ; -1            ;
; Maximum Number of M4K Memory Blocks                                ; -1           ; -1            ;
; Maximum Number of M-RAM Memory Blocks                              ; -1           ; -1            ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off          ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                 ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                        ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; Y2Cb.v                           ; yes             ; User Verilog HDL File              ; D:/RedLogic/VBuffer/Y2Cb.v                                          ;
; rom_color_gen_rgb.v              ; yes             ; User Verilog HDL File              ; D:/RedLogic/VBuffer/rom_color_gen_rgb.v                             ;
; ram256_32to1k_8.v                ; yes             ; User Verilog HDL File              ; D:/RedLogic/VBuffer/ram256_32to1k_8.v                               ;
; ram2k_2to512_8.v                 ; yes             ; User Verilog HDL File              ; D:/RedLogic/VBuffer/ram2k_2to512_8.v                                ;
; arbiter.v                        ; yes             ; User Verilog HDL File              ; D:/RedLogic/VBuffer/arbiter.v                                       ;
; rom_sel.v                        ; yes             ; User Verilog HDL File              ; D:/RedLogic/VBuffer/rom_sel.v                                       ;
; ram512_32.v                      ; yes             ; User Verilog HDL File              ; D:/RedLogic/VBuffer/ram512_32.v                                     ;
; rom2p017_cb.v                    ; yes             ; User Verilog HDL File              ; D:/RedLogic/VBuffer/rom2p017_cb.v                                   ;
; rom0p813_cr.v                    ; yes             ; User Verilog HDL File              ; D:/RedLogic/VBuffer/rom0p813_cr.v                                   ;
; rom1p164_y.v                     ; yes             ; User Verilog HDL File              ; D:/RedLogic/VBuffer/rom1p164_y.v                                    ;