i2c_altera.tan.rpt

视频采集

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Type                                                   ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                         ; To                                                                                                                                         ; From Clock                              ; To Clock                                ; Failed Paths ;
+--------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Worst-case tsu                                         ; N/A       ; None                             ; 11.931 ns                        ; SDRAM_DQ[25]                                                                                                                                 ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|DATAOUT[25]                                                                                     ;                                         ; SYSCLK                                  ; 0            ;
; Worst-case tco                                         ; N/A       ; None                             ; 12.513 ns                        ; mesure_card_top:inst5|sender_video:sender_video0|pixel_out[3]                                                                                ; ENC_DATA[3]                                                                                                                                ; PCLK                                    ;                                         ; 0            ;
; Worst-case tpd                                         ; N/A       ; None                             ; 5.487 ns                         ; PCLK                                                                                                                                         ; ENC_CLK                                                                                                                                    ;                                         ;                                         ; 0            ;
; Worst-case th                                          ; N/A       ; None                             ; 2.011 ns                         ; RST                                                                                                                                          ; filter:inst8|rst_out                                                                                                                       ;                                         ; SYSCLK                                  ; 0            ;
; Clock Setup: 'SYSCLK'                                  ; -5.758 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; i2c_cmd:inst|rom_addr[3]                                                                                                                     ; SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg3                                ; PLL:inst3|altpll:altpll_component|_clk0 ; SYSCLK                                  ; 14           ;
; Clock Setup: 'PLL:inst3|altpll:altpll_component|_clk0' ; 0.769 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; filter:inst8|rst_out                                                                                                                         ; i2c_cmd:inst|rom_addr[0]                                                                                                                   ; SYSCLK                                  ; PLL:inst3|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'PLL:inst3|altpll:altpll_component|_clk1' ; 19.923 ns ; 40.00 MHz ( period = 25.000 ns ) ; 196.97 MHz ( period = 5.077 ns ) ; mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|ram_block1a7~portb_address_reg8 ; mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7]                                                                                       ; PLL:inst3|altpll:altpll_component|_clk1 ; PLL:inst3|altpll:altpll_component|_clk1 ; 0            ;
; Clock Setup: 'PCLK'                                    ; N/A       ; None                             ; 127.63 MHz ( period = 7.835 ns ) ; mesure_card_top:inst5|receiver:receiver1|r_ram_wab[3]                                                                                        ; mesure_card_top:inst5|receiver:receiver1|r_req_video                                                                                       ; PCLK                                    ; PCLK                                    ; 0            ;
; Clock Hold: 'PLL:inst3|altpll:altpll_component|_clk0'  ; 0.822 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; mesure_card_top:inst5|datacnl:datacnl1|w_ba[1]                                                                                               ; mesure_card_top:inst5|datacnl:datacnl1|w_ba[1]                                                                                             ; PLL:inst3|altpll:altpll_component|_clk0 ; PLL:inst3|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'SYSCLK'                                   ; 1.039 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; Led_run:inst21|Mega_cnt[23]                                                                                                                  ; Led_run:inst21|Mega_cnt[23]                                                                                                                ; SYSCLK                                  ; SYSCLK                                  ; 0            ;
; Clock Hold: 'PLL:inst3|altpll:altpll_component|_clk1'  ; 1.928 ns  ; 40.00 MHz ( period = 25.000 ns ) ; N/A                              ; mesure_card_top:inst5|arbiter:arbiter0|ram_wab_reg[0]                                                                                        ; mesure_card_top:inst5|ram2k_2to512_8:ram_r3|altsyncram:altsyncram_component|altsyncram_8851:auto_generated|ram_block1a1~porta_address_reg0 ; PLL:inst3|altpll:altpll_component|_clk1 ; PLL:inst3|altpll:altpll_component|_clk1 ; 0            ;
; Total number of failed paths                           ;           ;                                  ;                                  ;                                                                                                                                              ;                                                                                                                                            ;                                         ;                                         ; 14           ;
+--------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;