📄 i2c_altera.fit.rpt
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; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[1] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[0] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[1] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[0] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram2k_2to512_8:ram_r3|altsyncram:altsyncram_component|altsyncram_8851:auto_generated|q_b[1] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram2k_2to512_8:ram_r3|altsyncram:altsyncram_component|altsyncram_8851:auto_generated|q_b[0] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sender_video:sender_video0|pixel_out[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[7] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sender_video:sender_video0|pixel_out[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[6] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sender_video:sender_video0|pixel_out[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[5] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sender_video:sender_video0|pixel_out[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[4] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sender_video:sender_video0|pixel_out[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[3] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sender_video:sender_video0|pixel_out[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[2] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sender_video:sender_video0|pixel_out[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[1] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sender_video:sender_video0|pixel_out[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[0] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[30] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[6] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[29] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[5] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[28] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[4] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[27] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[3] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[26] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[2] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[25] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[1] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[24] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[0] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[23] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[7] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[22] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[6] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[21] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[5] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[20] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[4] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[19] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[3] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[18] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[2] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[17] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[1] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[16] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[0] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[15] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[7] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[14] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[6] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[13] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[5] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[12] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[4] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[11] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[3] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[10] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[2] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[1] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[0] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component|altsyncram_l951:auto_generated|q_b[7] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component|altsyncram_l951:auto_generated|q_b[6] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component|altsyncram_l951:auto_generated|q_b[5] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component|altsyncram_l951:auto_generated|q_b[4] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component|altsyncram_l951:auto_generated|q_b[3] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component|altsyncram_l951:auto_generated|q_b[2] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component|altsyncram_l951:auto_generated|q_b[1] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component|altsyncram_l951:auto_generated|q_b[0] ; PORTBDATAOUT ;
; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[31] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; mesure_card_top:inst5|sdr_sdram:sdr_sdram1|sdr_data_path:data_path1|DIN1[7] ; PORTBDATAOUT ;
+-----------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+---------------------------------------------------------------------------------------------------------------------+------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/RedLogic/VBuffer/I2C_ALTERA.fit.eqn.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/RedLogic/VBuffer/I2C_ALTERA.pin.
+---------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+-----------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------------------------+
; Total logic elements ; 1,202 / 12,060 ( 9 % ) ;
; -- Combinational with no register ; 329 ;
; -- Register only ; 252 ;
; -- Combinational with a register ; 621 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 362 ;
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