sender.v

视频采集

module sender(
	clk50m,
	rst,
	
	req,
	ack,
	data,
	dck,
	
	s_ram_rab,
	s_ram_rdb,
	s_req,
	s_ack,
	s_start,
	s_finish,
	
	vsin
	);

input	clk50m;
input	rst;

output	req;
output	data;
output	dck;
input	ack;

output	[12:0]	s_ram_rab;
output	s_req;
input	s_ram_rdb;
input	s_ack;
input	s_finish;
input	s_start;
input	vsin;

reg	vsin_reg,vsin_reg1,vsin_reg2;
reg	ack_reg;

always @ (posedge clk50m) begin
vsin_reg1 <= vsin;
vsin_reg2 <= vsin_reg1;
vsin_reg <= vsin_reg2;
ack_reg <= ack;
end

/*************************************************************************/	
reg	[11:0]	s_ram_rab_reg;
always @ (posedge clk50m or negedge rst)
if(!rst)
	s_ram_rab_reg <= 0;
else if(ack) begin
	if(s_ram_rab_reg == 'd2880)
		s_ram_rab_reg <= 0;
	else
		s_ram_rab_reg <= s_ram_rab_reg + 1;
	end
else if(!vsin_reg)
	s_ram_rab_reg <= 0;
	
reg	s_ram_rab_hbit;
always @ (posedge clk50m or negedge rst)
if(!rst)
	s_ram_rab_hbit <= 0;
else if(s_ram_rab_reg == 'd2880)
	s_ram_rab_hbit <= ~s_ram_rab_hbit;
else if(!vsin_reg)
	s_ram_rab_hbit <= 0;

wire	[12:0]	s_ram_rab = {s_ram_rab_hbit,s_ram_rab_reg};
	
reg	s_req;
always @ (posedge clk50m or negedge rst)
if(!rst)
	s_req <= 0;
else if((!vsin_reg & vsin_reg2) || s_ram_rab_reg == 'd10 && !s_finish)
	s_req <= 1;
else if(s_ack)
	s_req <= 0;

reg data;
always @ (posedge clk50m)
data <= s_ram_rdb;

wire dck = ack_reg?clk50m:'d1;

reg	req;
always @ (posedge clk50m or negedge rst)
if(!rst)
	req <= 0;
else if(s_start)
	req <= 1;
else if(s_finish && s_ram_rab == 'd6974)//'d6975
	req <= 0;
endmodule