i2c_altera.map.eqn

视频采集

--SB1_qd_reg_dly1[1] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[1]
--operation mode is normal

SB1_qd_reg_dly1[1]_lut_out = H1L55Q & H1_qd_dly[1] # !H1L55Q & (H1L45Q & H1_qd_dly[1] # !H1L45Q & (H1_qd_dly1[1]));
SB1_qd_reg_dly1[1] = DFFEAS(SB1_qd_reg_dly1[1]_lut_out, PCLK, VCC, , , , , , );


--YB1_q_b[0] is mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 256, Port A Width: 4, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_b[0]_PORT_A_data_in = BUS(CB1_s_ram_wdb[0], CB1_s_ram_wdb[8], CB1_s_ram_wdb[16], CB1_s_ram_wdb[24]);
YB1_q_b[0]_PORT_A_data_in_reg = DFFE(YB1_q_b[0]_PORT_A_data_in, YB1_q_b[0]_clock_0, , , YB1_q_b[0]_clock_enable_0);
YB1_q_b[0]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
YB1_q_b[0]_PORT_A_address_reg = DFFE(YB1_q_b[0]_PORT_A_address, YB1_q_b[0]_clock_0, , , YB1_q_b[0]_clock_enable_0);
YB1_q_b[0]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
YB1_q_b[0]_PORT_B_address_reg = DFFE(YB1_q_b[0]_PORT_B_address, YB1_q_b[0]_clock_1, , , );
YB1_q_b[0]_PORT_A_write_enable = VCC;
YB1_q_b[0]_PORT_A_write_enable_reg = DFFE(YB1_q_b[0]_PORT_A_write_enable, YB1_q_b[0]_clock_0, , , YB1_q_b[0]_clock_enable_0);
YB1_q_b[0]_PORT_B_read_enable = VCC;
YB1_q_b[0]_PORT_B_read_enable_reg = DFFE(YB1_q_b[0]_PORT_B_read_enable, YB1_q_b[0]_clock_1, , , );
YB1_q_b[0]_clock_0 = Z1__clk0;
YB1_q_b[0]_clock_1 = PCLK;
YB1_q_b[0]_clock_enable_0 = CB1_s_enable;
YB1_q_b[0]_PORT_B_data_out = MEMORY(YB1_q_b[0]_PORT_A_data_in_reg, , YB1_q_b[0]_PORT_A_address_reg, YB1_q_b[0]_PORT_B_address_reg, YB1_q_b[0]_PORT_A_write_enable_reg, YB1_q_b[0]_PORT_B_read_enable_reg, , , YB1_q_b[0]_clock_0, YB1_q_b[0]_clock_1, YB1_q_b[0]_clock_enable_0, , , );
YB1_q_b[0] = YB1_q_b[0]_PORT_B_data_out[0];


--SB1_qd_reg_dly1[0] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[0]
--operation mode is normal

SB1_qd_reg_dly1[0]_lut_out = H1L55Q & H1_qd_dly[0] # !H1L55Q & (H1L45Q & H1_qd_dly[0] # !H1L45Q & (H1_qd_dly1[0]));
SB1_qd_reg_dly1[0] = DFFEAS(SB1_qd_reg_dly1[0]_lut_out, PCLK, VCC, , , , , , );


--N1_dir is Led_run:inst21|dir
--operation mode is normal

N1_dir_lut_out = N1_dir & (N1_led[2] # N1_led[1] # !N1L05) # !N1_dir & N1_led[2] & N1_led[1] & N1L05;
N1_dir = DFFEAS(N1_dir_lut_out, N1_Mega_cnt[23], RST, , , , , , );


--N1_Mega_cnt[23] is Led_run:inst21|Mega_cnt[23]
--operation mode is normal

N1_Mega_cnt[23]_carry_eqn = N1L74;
N1_Mega_cnt[23]_lut_out = N1_Mega_cnt[23] $ (N1_Mega_cnt[23]_carry_eqn);
N1_Mega_cnt[23] = DFFEAS(N1_Mega_cnt[23]_lut_out, SYSCLK, RST, , , , , , );


--DC1_SA[10] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[10]
--operation mode is normal

DC1_SA[10]_lut_out = DC1_do_rw & (!EC1_SC_PM) # !DC1_do_rw & (DC1_do_precharge & (!EC1_SC_PM) # !DC1_do_precharge & DC1L52);
DC1_SA[10] = DFFEAS(DC1_SA[10]_lut_out, Z1__clk0, VCC, , , , , !RST, );


--DC1_SA[9] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[9]
--operation mode is normal

DC1_SA[9]_lut_out = RST & EC1_SADDR[17] & (DC1_do_writea # DC1_do_reada);
DC1_SA[9] = DFFEAS(DC1_SA[9]_lut_out, Z1__clk0, VCC, , , , , , );


--DC1_SA[8] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[8]
--operation mode is normal

DC1_SA[8]_lut_out = RST & EC1_SADDR[16] & (DC1_do_writea # DC1_do_reada);
DC1_SA[8] = DFFEAS(DC1_SA[8]_lut_out, Z1__clk0, VCC, , , , , , );


--DC1_SA[7] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[7]
--operation mode is normal

DC1_SA[7]_lut_out = DC1_do_writea & (EC1_SADDR[15]) # !DC1_do_writea & (DC1_do_reada & (EC1_SADDR[15]) # !DC1_do_reada & EC1_SADDR[7]);
DC1_SA[7] = DFFEAS(DC1_SA[7]_lut_out, Z1__clk0, VCC, , , , , !RST, );


--DC1_SA[6] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[6]
--operation mode is normal

DC1_SA[6]_lut_out = DC1_do_writea & (EC1_SADDR[14]) # !DC1_do_writea & (DC1_do_reada & (EC1_SADDR[14]) # !DC1_do_reada & EC1_SADDR[7]);
DC1_SA[6] = DFFEAS(DC1_SA[6]_lut_out, Z1__clk0, VCC, , , , , !RST, );


--DC1_SA[5] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[5]
--operation mode is normal

DC1_SA[5]_lut_out = DC1_do_writea & (EC1_SADDR[13]) # !DC1_do_writea & (DC1_do_reada & (EC1_SADDR[13]) # !DC1_do_reada & EC1_SADDR[5]);
DC1_SA[5] = DFFEAS(DC1_SA[5]_lut_out, Z1__clk0, VCC, , , , , !RST, );


--DC1_SA[4] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[4]
--operation mode is normal

DC1_SA[4]_lut_out = DC1_do_writea & (EC1_SADDR[12]) # !DC1_do_writea & (DC1_do_reada & (EC1_SADDR[12]) # !DC1_do_reada & EC1_SADDR[4]);
DC1_SA[4] = DFFEAS(DC1_SA[4]_lut_out, Z1__clk0, VCC, , , , , !RST, );


--DC1_SA[3] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[3]
--operation mode is normal

DC1_SA[3]_lut_out = DC1_do_writea & (EC1_SADDR[11]) # !DC1_do_writea & (DC1_do_reada & (EC1_SADDR[11]) # !DC1_do_reada & EC1_SADDR[3]);
DC1_SA[3] = DFFEAS(DC1_SA[3]_lut_out, Z1__clk0, VCC, , , , , !RST, );


--DC1_SA[2] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[2]
--operation mode is normal

DC1_SA[2]_lut_out = DC1_do_writea & (EC1_SADDR[10]) # !DC1_do_writea & (DC1_do_reada & (EC1_SADDR[10]) # !DC1_do_reada & EC1_SADDR[5]);
DC1_SA[2] = DFFEAS(DC1_SA[2]_lut_out, Z1__clk0, VCC, , , , , !RST, );


--DC1_SA[1] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[1]
--operation mode is normal

DC1_SA[1]_lut_out = DC1_do_writea & (EC1_SADDR[9]) # !DC1_do_writea & (DC1_do_reada & (EC1_SADDR[9]) # !DC1_do_reada & EC1_SADDR[5]);
DC1_SA[1] = DFFEAS(DC1_SA[1]_lut_out, Z1__clk0, VCC, , , , , !RST, );


--DC1_SA[0] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|SA[0]
--operation mode is normal

DC1_SA[0]_lut_out = DC1_do_writea & (EC1_SADDR[8]) # !DC1_do_writea & (DC1_do_reada & (EC1_SADDR[8]) # !DC1_do_reada & EC1_SADDR[0]);
DC1_SA[0] = DFFEAS(DC1_SA[0]_lut_out, Z1__clk0, VCC, , , , , !RST, );


--DC1_BA[1] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|BA[1]
--operation mode is normal

DC1_BA[1]_lut_out = RST & EC1_SADDR[20] & (!DC1_do_load_mode);
DC1_BA[1] = DFFEAS(DC1_BA[1]_lut_out, Z1__clk0, VCC, , , , , , );


--DC1_BA[0] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|BA[0]
--operation mode is normal

DC1_BA[0]_lut_out = RST & EC1_SADDR[19] & (!DC1_do_load_mode);
DC1_BA[0] = DFFEAS(DC1_BA[0]_lut_out, Z1__clk0, VCC, , , , , , );


--DC1_do_precharge is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|do_precharge
--operation mode is normal

DC1_do_precharge_lut_out = EC1_PRECHARGE & (!DC1_do_precharge & !DC1_command_done);
DC1_do_precharge = DFFEAS(DC1_do_precharge_lut_out, Z1__clk0, RST, , , , , , );


--DC1_do_writea is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|do_writea
--operation mode is normal

DC1_do_writea_lut_out = DC1L92;
DC1_do_writea = DFFEAS(DC1_do_writea_lut_out, Z1__clk0, RST, , , , , , );


--DC1_do_reada is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|do_reada
--operation mode is normal

DC1_do_reada_lut_out = DC1L13 & EC1_READA & !DC1_do_reada & !EC1_timer_zero;
DC1_do_reada = DFFEAS(DC1_do_reada_lut_out, Z1__clk0, RST, , , , , , );


--DC1L53 is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|always4~0
--operation mode is normal

DC1L53 = !DC1_do_writea & !DC1_do_reada;


--DC1_do_rw is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|do_rw
--operation mode is normal

DC1_do_rw_lut_out = DC1_rw_shift[0];
DC1_do_rw = DFFEAS(DC1_do_rw_lut_out, Z1__clk0, RST, , DC1L53, , , , );


--DC1_do_load_mode is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|do_load_mode
--operation mode is normal

DC1_do_load_mode_lut_out = EC1_LOAD_MODE & (!DC1_do_load_mode & !DC1_command_done);
DC1_do_load_mode = DFFEAS(DC1_do_load_mode_lut_out, Z1__clk0, RST, , , , , , );


--DC1L5 is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|CAS_N~62
--operation mode is normal

DC1L5 = DC1_do_precharge # !DC1_do_load_mode & (!DC1_do_rw # !DC1L53);


--DC1_rw_flag is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|rw_flag
--operation mode is normal

DC1_rw_flag_lut_out = DC1_do_reada;
DC1_rw_flag = DFFEAS(DC1_rw_flag_lut_out, Z1__clk0, RST, , DC1L43, , , , );


--DC1_oe4 is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|oe4
--operation mode is normal

DC1_oe4_lut_out = DC1_do_writea1 # DC1_oe4 & DC1L23 & !DC1_do_precharge;
DC1_oe4 = DFFEAS(DC1_oe4_lut_out, Z1__clk0, RST, , , , , , );


--DC1L63 is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|always4~37
--operation mode is normal

DC1L63 = DC1_do_precharge & (DC1_rw_flag # DC1_oe4);


--DC1_do_refresh is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|do_refresh
--operation mode is normal

DC1_do_refresh_lut_out = DC1L03 & DC1L23 & (EC1_timer_zero # EC1_REFRESH);
DC1_do_refresh = DFFEAS(DC1_do_refresh_lut_out, Z1__clk0, RST, , , , , , );


--DC1L11 is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|RAS_N~20
--operation mode is normal

DC1L11 = DC1_do_precharge # DC1_do_load_mode # DC1_do_writea # DC1_do_reada;


--DC1L72 is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|WE_N~55
--operation mode is normal

DC1L72 = !DC1_do_precharge & !DC1_do_load_mode;


--DC1L82 is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|WE_N~56
--operation mode is normal

DC1L82 = DC1L72 & (DC1_rw_flag # !DC1_do_rw # !DC1L53);


--CB1_s_enable is mesure_card_top:inst5|datacnl:datacnl1|s_enable
--operation mode is normal

CB1_s_enable_lut_out = CB1L631;
CB1_s_enable = DFFEAS(CB1_s_enable_lut_out, Z1__clk0, RST, , CB1L15, , , , );


--CB1_s_ram_wdb[7] is mesure_card_top:inst5|datacnl:datacnl1|s_ram_wdb[7]
--operation mode is normal

CB1_s_ram_wdb[7]_lut_out = PB1_DATAOUT[7];
CB1_s_ram_wdb[7] = DFFEAS(CB1_s_ram_wdb[7]_lut_out, Z1__clk0, VCC, , , , , , );


--CB1_s_ram_wdb[15] is mesure_card_top:inst5|datacnl:datacnl1|s_ram_wdb[15]
--operation mode is normal