i2c_altera.map.eqn

视频采集

--UC1_safe_q[0] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[0]
--operation mode is arithmetic

UC1_safe_q[0]_lut_out = !UC1_safe_q[0];
UC1_safe_q[0] = DFFEAS(UC1_safe_q[0]_lut_out, PCLK, VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L4 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella0~COUT
--operation mode is arithmetic

UC1L4 = CARRY(UC1_safe_q[0]);


--UC1_safe_q[1] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[1]
--operation mode is arithmetic

UC1_safe_q[1]_carry_eqn = UC1L4;
UC1_safe_q[1]_lut_out = UC1_safe_q[1] $ (UC1_safe_q[1]_carry_eqn);
UC1_safe_q[1] = DFFEAS(UC1_safe_q[1]_lut_out, PCLK, VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L6 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella1~COUT
--operation mode is arithmetic

UC1L6 = CARRY(!UC1L4 # !UC1_safe_q[1]);


--UC1_safe_q[2] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[2]
--operation mode is arithmetic

UC1_safe_q[2]_carry_eqn = UC1L6;
UC1_safe_q[2]_lut_out = UC1_safe_q[2] $ (!UC1_safe_q[2]_carry_eqn);
UC1_safe_q[2] = DFFEAS(UC1_safe_q[2]_lut_out, PCLK, VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L8 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella2~COUT
--operation mode is arithmetic

UC1L8 = CARRY(UC1_safe_q[2] & (!UC1L6));


--UC1_safe_q[3] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[3]
--operation mode is arithmetic

UC1_safe_q[3]_carry_eqn = UC1L8;
UC1_safe_q[3]_lut_out = UC1_safe_q[3] $ (UC1_safe_q[3]_carry_eqn);
UC1_safe_q[3] = DFFEAS(UC1_safe_q[3]_lut_out, PCLK, VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L01 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella3~COUT
--operation mode is arithmetic

UC1L01 = CARRY(!UC1L8 # !UC1_safe_q[3]);


--UC1_safe_q[4] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[4]
--operation mode is arithmetic

UC1_safe_q[4]_carry_eqn = UC1L01;
UC1_safe_q[4]_lut_out = UC1_safe_q[4] $ (!UC1_safe_q[4]_carry_eqn);
UC1_safe_q[4] = DFFEAS(UC1_safe_q[4]_lut_out, PCLK, VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L21 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella4~COUT
--operation mode is arithmetic

UC1L21 = CARRY(UC1_safe_q[4] & (!UC1L01));


--UC1_safe_q[5] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|safe_q[5]
--operation mode is arithmetic

UC1_safe_q[5]_carry_eqn = UC1L21;
UC1_safe_q[5]_lut_out = UC1_safe_q[5] $ (UC1_safe_q[5]_carry_eqn);
UC1_safe_q[5] = DFFEAS(UC1_safe_q[5]_lut_out, PCLK, VCC, , , ~GND, , , UC1_modulus_trigger);

--UC1L41 is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|cntr_ngc:cntr1|counter_cella5~COUT
--operation mode is arithmetic

UC1L41 = CARRY(!UC1L21 # !UC1_safe_q[5]);


--SB1_blank_dly35 is mesure_card_top:inst5|sender_video:sender_video0|blank_dly35
--operation mode is normal

SB1_blank_dly35_lut_out = SB1_blank_dly34;
SB1_blank_dly35 = DFFEAS(SB1_blank_dly35_lut_out, PCLK, VCC, , , , , , );


--YB1_q_b[6] is mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 256, Port A Width: 4, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_b[6]_PORT_A_data_in = BUS(CB1_s_ram_wdb[6], CB1_s_ram_wdb[14], CB1_s_ram_wdb[22], CB1_s_ram_wdb[30]);
YB1_q_b[6]_PORT_A_data_in_reg = DFFE(YB1_q_b[6]_PORT_A_data_in, YB1_q_b[6]_clock_0, , , YB1_q_b[6]_clock_enable_0);
YB1_q_b[6]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
YB1_q_b[6]_PORT_A_address_reg = DFFE(YB1_q_b[6]_PORT_A_address, YB1_q_b[6]_clock_0, , , YB1_q_b[6]_clock_enable_0);
YB1_q_b[6]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
YB1_q_b[6]_PORT_B_address_reg = DFFE(YB1_q_b[6]_PORT_B_address, YB1_q_b[6]_clock_1, , , );
YB1_q_b[6]_PORT_A_write_enable = VCC;
YB1_q_b[6]_PORT_A_write_enable_reg = DFFE(YB1_q_b[6]_PORT_A_write_enable, YB1_q_b[6]_clock_0, , , YB1_q_b[6]_clock_enable_0);
YB1_q_b[6]_PORT_B_read_enable = VCC;
YB1_q_b[6]_PORT_B_read_enable_reg = DFFE(YB1_q_b[6]_PORT_B_read_enable, YB1_q_b[6]_clock_1, , , );
YB1_q_b[6]_clock_0 = Z1__clk0;
YB1_q_b[6]_clock_1 = PCLK;
YB1_q_b[6]_clock_enable_0 = CB1_s_enable;
YB1_q_b[6]_PORT_B_data_out = MEMORY(YB1_q_b[6]_PORT_A_data_in_reg, , YB1_q_b[6]_PORT_A_address_reg, YB1_q_b[6]_PORT_B_address_reg, YB1_q_b[6]_PORT_A_write_enable_reg, YB1_q_b[6]_PORT_B_read_enable_reg, , , YB1_q_b[6]_clock_0, YB1_q_b[6]_clock_1, YB1_q_b[6]_clock_enable_0, , , );
YB1_q_b[6] = YB1_q_b[6]_PORT_B_data_out[0];


--SB1_qd_reg_dly1[6] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[6]
--operation mode is normal

SB1_qd_reg_dly1[6]_lut_out = H1L55Q & H1_qd_dly[6] # !H1L55Q & (H1L45Q & H1_qd_dly[6] # !H1L45Q & (H1_qd_dly1[6]));
SB1_qd_reg_dly1[6] = DFFEAS(SB1_qd_reg_dly1[6]_lut_out, PCLK, VCC, , , , , , );


--YB1_q_b[5] is mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 256, Port A Width: 4, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_b[5]_PORT_A_data_in = BUS(CB1_s_ram_wdb[5], CB1_s_ram_wdb[13], CB1_s_ram_wdb[21], CB1_s_ram_wdb[29]);
YB1_q_b[5]_PORT_A_data_in_reg = DFFE(YB1_q_b[5]_PORT_A_data_in, YB1_q_b[5]_clock_0, , , YB1_q_b[5]_clock_enable_0);
YB1_q_b[5]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
YB1_q_b[5]_PORT_A_address_reg = DFFE(YB1_q_b[5]_PORT_A_address, YB1_q_b[5]_clock_0, , , YB1_q_b[5]_clock_enable_0);
YB1_q_b[5]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
YB1_q_b[5]_PORT_B_address_reg = DFFE(YB1_q_b[5]_PORT_B_address, YB1_q_b[5]_clock_1, , , );
YB1_q_b[5]_PORT_A_write_enable = VCC;
YB1_q_b[5]_PORT_A_write_enable_reg = DFFE(YB1_q_b[5]_PORT_A_write_enable, YB1_q_b[5]_clock_0, , , YB1_q_b[5]_clock_enable_0);
YB1_q_b[5]_PORT_B_read_enable = VCC;
YB1_q_b[5]_PORT_B_read_enable_reg = DFFE(YB1_q_b[5]_PORT_B_read_enable, YB1_q_b[5]_clock_1, , , );
YB1_q_b[5]_clock_0 = Z1__clk0;
YB1_q_b[5]_clock_1 = PCLK;
YB1_q_b[5]_clock_enable_0 = CB1_s_enable;
YB1_q_b[5]_PORT_B_data_out = MEMORY(YB1_q_b[5]_PORT_A_data_in_reg, , YB1_q_b[5]_PORT_A_address_reg, YB1_q_b[5]_PORT_B_address_reg, YB1_q_b[5]_PORT_A_write_enable_reg, YB1_q_b[5]_PORT_B_read_enable_reg, , , YB1_q_b[5]_clock_0, YB1_q_b[5]_clock_1, YB1_q_b[5]_clock_enable_0, , , );
YB1_q_b[5] = YB1_q_b[5]_PORT_B_data_out[0];


--SB1_qd_reg_dly1[5] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[5]
--operation mode is normal

SB1_qd_reg_dly1[5]_lut_out = H1L55Q & H1_qd_dly[5] # !H1L55Q & (H1L45Q & H1_qd_dly[5] # !H1L45Q & (H1_qd_dly1[5]));
SB1_qd_reg_dly1[5] = DFFEAS(SB1_qd_reg_dly1[5]_lut_out, PCLK, VCC, , , , , , );


--YB1_q_b[4] is mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 256, Port A Width: 4, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_b[4]_PORT_A_data_in = BUS(CB1_s_ram_wdb[4], CB1_s_ram_wdb[12], CB1_s_ram_wdb[20], CB1_s_ram_wdb[28]);
YB1_q_b[4]_PORT_A_data_in_reg = DFFE(YB1_q_b[4]_PORT_A_data_in, YB1_q_b[4]_clock_0, , , YB1_q_b[4]_clock_enable_0);
YB1_q_b[4]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
YB1_q_b[4]_PORT_A_address_reg = DFFE(YB1_q_b[4]_PORT_A_address, YB1_q_b[4]_clock_0, , , YB1_q_b[4]_clock_enable_0);
YB1_q_b[4]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
YB1_q_b[4]_PORT_B_address_reg = DFFE(YB1_q_b[4]_PORT_B_address, YB1_q_b[4]_clock_1, , , );
YB1_q_b[4]_PORT_A_write_enable = VCC;
YB1_q_b[4]_PORT_A_write_enable_reg = DFFE(YB1_q_b[4]_PORT_A_write_enable, YB1_q_b[4]_clock_0, , , YB1_q_b[4]_clock_enable_0);
YB1_q_b[4]_PORT_B_read_enable = VCC;
YB1_q_b[4]_PORT_B_read_enable_reg = DFFE(YB1_q_b[4]_PORT_B_read_enable, YB1_q_b[4]_clock_1, , , );
YB1_q_b[4]_clock_0 = Z1__clk0;
YB1_q_b[4]_clock_1 = PCLK;
YB1_q_b[4]_clock_enable_0 = CB1_s_enable;
YB1_q_b[4]_PORT_B_data_out = MEMORY(YB1_q_b[4]_PORT_A_data_in_reg, , YB1_q_b[4]_PORT_A_address_reg, YB1_q_b[4]_PORT_B_address_reg, YB1_q_b[4]_PORT_A_write_enable_reg, YB1_q_b[4]_PORT_B_read_enable_reg, , , YB1_q_b[4]_clock_0, YB1_q_b[4]_clock_1, YB1_q_b[4]_clock_enable_0, , , );
YB1_q_b[4] = YB1_q_b[4]_PORT_B_data_out[0];


--SB1_qd_reg_dly1[4] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[4]
--operation mode is normal

SB1_qd_reg_dly1[4]_lut_out = H1L55Q & H1_qd_dly[4] # !H1L55Q & (H1L45Q & H1_qd_dly[4] # !H1L45Q & (H1_qd_dly1[4]));
SB1_qd_reg_dly1[4] = DFFEAS(SB1_qd_reg_dly1[4]_lut_out, PCLK, VCC, , , , , , );


--YB1_q_b[3] is mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 256, Port A Width: 4, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_b[3]_PORT_A_data_in = BUS(CB1_s_ram_wdb[3], CB1_s_ram_wdb[11], CB1_s_ram_wdb[19], CB1_s_ram_wdb[27]);
YB1_q_b[3]_PORT_A_data_in_reg = DFFE(YB1_q_b[3]_PORT_A_data_in, YB1_q_b[3]_clock_0, , , YB1_q_b[3]_clock_enable_0);
YB1_q_b[3]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
YB1_q_b[3]_PORT_A_address_reg = DFFE(YB1_q_b[3]_PORT_A_address, YB1_q_b[3]_clock_0, , , YB1_q_b[3]_clock_enable_0);
YB1_q_b[3]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
YB1_q_b[3]_PORT_B_address_reg = DFFE(YB1_q_b[3]_PORT_B_address, YB1_q_b[3]_clock_1, , , );
YB1_q_b[3]_PORT_A_write_enable = VCC;
YB1_q_b[3]_PORT_A_write_enable_reg = DFFE(YB1_q_b[3]_PORT_A_write_enable, YB1_q_b[3]_clock_0, , , YB1_q_b[3]_clock_enable_0);
YB1_q_b[3]_PORT_B_read_enable = VCC;
YB1_q_b[3]_PORT_B_read_enable_reg = DFFE(YB1_q_b[3]_PORT_B_read_enable, YB1_q_b[3]_clock_1, , , );
YB1_q_b[3]_clock_0 = Z1__clk0;
YB1_q_b[3]_clock_1 = PCLK;
YB1_q_b[3]_clock_enable_0 = CB1_s_enable;
YB1_q_b[3]_PORT_B_data_out = MEMORY(YB1_q_b[3]_PORT_A_data_in_reg, , YB1_q_b[3]_PORT_A_address_reg, YB1_q_b[3]_PORT_B_address_reg, YB1_q_b[3]_PORT_A_write_enable_reg, YB1_q_b[3]_PORT_B_read_enable_reg, , , YB1_q_b[3]_clock_0, YB1_q_b[3]_clock_1, YB1_q_b[3]_clock_enable_0, , , );
YB1_q_b[3] = YB1_q_b[3]_PORT_B_data_out[0];


--SB1_qd_reg_dly1[3] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[3]
--operation mode is normal

SB1_qd_reg_dly1[3]_lut_out = H1L55Q & H1_qd_dly[3] # !H1L55Q & (H1L45Q & H1_qd_dly[3] # !H1L45Q & (H1_qd_dly1[3]));
SB1_qd_reg_dly1[3] = DFFEAS(SB1_qd_reg_dly1[3]_lut_out, PCLK, VCC, , , , , , );


--YB1_q_b[2] is mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 256, Port A Width: 4, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_b[2]_PORT_A_data_in = BUS(CB1_s_ram_wdb[2], CB1_s_ram_wdb[10], CB1_s_ram_wdb[18], CB1_s_ram_wdb[26]);
YB1_q_b[2]_PORT_A_data_in_reg = DFFE(YB1_q_b[2]_PORT_A_data_in, YB1_q_b[2]_clock_0, , , YB1_q_b[2]_clock_enable_0);
YB1_q_b[2]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
YB1_q_b[2]_PORT_A_address_reg = DFFE(YB1_q_b[2]_PORT_A_address, YB1_q_b[2]_clock_0, , , YB1_q_b[2]_clock_enable_0);
YB1_q_b[2]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
YB1_q_b[2]_PORT_B_address_reg = DFFE(YB1_q_b[2]_PORT_B_address, YB1_q_b[2]_clock_1, , , );
YB1_q_b[2]_PORT_A_write_enable = VCC;
YB1_q_b[2]_PORT_A_write_enable_reg = DFFE(YB1_q_b[2]_PORT_A_write_enable, YB1_q_b[2]_clock_0, , , YB1_q_b[2]_clock_enable_0);
YB1_q_b[2]_PORT_B_read_enable = VCC;
YB1_q_b[2]_PORT_B_read_enable_reg = DFFE(YB1_q_b[2]_PORT_B_read_enable, YB1_q_b[2]_clock_1, , , );
YB1_q_b[2]_clock_0 = Z1__clk0;
YB1_q_b[2]_clock_1 = PCLK;
YB1_q_b[2]_clock_enable_0 = CB1_s_enable;
YB1_q_b[2]_PORT_B_data_out = MEMORY(YB1_q_b[2]_PORT_A_data_in_reg, , YB1_q_b[2]_PORT_A_address_reg, YB1_q_b[2]_PORT_B_address_reg, YB1_q_b[2]_PORT_A_write_enable_reg, YB1_q_b[2]_PORT_B_read_enable_reg, , , YB1_q_b[2]_clock_0, YB1_q_b[2]_clock_1, YB1_q_b[2]_clock_enable_0, , , );
YB1_q_b[2] = YB1_q_b[2]_PORT_B_data_out[0];


--SB1_qd_reg_dly1[2] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[2]
--operation mode is normal

SB1_qd_reg_dly1[2]_lut_out = H1L55Q & H1_qd_dly[2] # !H1L55Q & (H1L45Q & H1_qd_dly[2] # !H1L45Q & (H1_qd_dly1[2]));
SB1_qd_reg_dly1[2] = DFFEAS(SB1_qd_reg_dly1[2]_lut_out, PCLK, VCC, , , , , , );


--YB1_q_b[1] is mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 256, Port A Width: 4, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_b[1]_PORT_A_data_in = BUS(CB1_s_ram_wdb[1], CB1_s_ram_wdb[9], CB1_s_ram_wdb[17], CB1_s_ram_wdb[25]);
YB1_q_b[1]_PORT_A_data_in_reg = DFFE(YB1_q_b[1]_PORT_A_data_in, YB1_q_b[1]_clock_0, , , YB1_q_b[1]_clock_enable_0);
YB1_q_b[1]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
YB1_q_b[1]_PORT_A_address_reg = DFFE(YB1_q_b[1]_PORT_A_address, YB1_q_b[1]_clock_0, , , YB1_q_b[1]_clock_enable_0);
YB1_q_b[1]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
YB1_q_b[1]_PORT_B_address_reg = DFFE(YB1_q_b[1]_PORT_B_address, YB1_q_b[1]_clock_1, , , );
YB1_q_b[1]_PORT_A_write_enable = VCC;
YB1_q_b[1]_PORT_A_write_enable_reg = DFFE(YB1_q_b[1]_PORT_A_write_enable, YB1_q_b[1]_clock_0, , , YB1_q_b[1]_clock_enable_0);
YB1_q_b[1]_PORT_B_read_enable = VCC;
YB1_q_b[1]_PORT_B_read_enable_reg = DFFE(YB1_q_b[1]_PORT_B_read_enable, YB1_q_b[1]_clock_1, , , );
YB1_q_b[1]_clock_0 = Z1__clk0;
YB1_q_b[1]_clock_1 = PCLK;
YB1_q_b[1]_clock_enable_0 = CB1_s_enable;
YB1_q_b[1]_PORT_B_data_out = MEMORY(YB1_q_b[1]_PORT_A_data_in_reg, , YB1_q_b[1]_PORT_A_address_reg, YB1_q_b[1]_PORT_B_address_reg, YB1_q_b[1]_PORT_A_write_enable_reg, YB1_q_b[1]_PORT_B_read_enable_reg, , , YB1_q_b[1]_clock_0, YB1_q_b[1]_clock_1, YB1_q_b[1]_clock_enable_0, , , );
YB1_q_b[1] = YB1_q_b[1]_PORT_B_data_out[0];