i2c_altera.map.eqn

视频采集

--SB1L14 is mesure_card_top:inst5|sender_video:sender_video0|pixel[2]~69
--operation mode is normal

SB1L14 = SB1_blank_dly36 & SB1_pixel_out[2] # !SB1_blank_dly36 & (TC1_q_b[5]);


--SB1_pixel_out[1] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[1]
--operation mode is normal

SB1_pixel_out[1]_lut_out = YB1_q_b[1];
SB1_pixel_out[1] = DFFEAS(SB1_pixel_out[1]_lut_out, PCLK, VCC, , , , , , );


--TC1_q_b[6] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 33, Port A Width: 1, Port B Depth: 33, Port B Width: 1
--Port A Logical Depth: 33, Port A Logical Width: 8, Port B Logical Depth: 33, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
TC1_q_b[6]_PORT_A_data_in = SB1_qd_reg_dly1[1];
TC1_q_b[6]_PORT_A_data_in_reg = DFFE(TC1_q_b[6]_PORT_A_data_in, TC1_q_b[6]_clock_0, , , );
TC1_q_b[6]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[6]_PORT_A_address_reg = DFFE(TC1_q_b[6]_PORT_A_address, TC1_q_b[6]_clock_0, , , );
TC1_q_b[6]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[6]_PORT_B_address_reg = DFFE(TC1_q_b[6]_PORT_B_address, TC1_q_b[6]_clock_0, , , );
TC1_q_b[6]_PORT_A_write_enable = VCC;
TC1_q_b[6]_PORT_A_write_enable_reg = DFFE(TC1_q_b[6]_PORT_A_write_enable, TC1_q_b[6]_clock_0, , , );
TC1_q_b[6]_PORT_B_read_enable = VCC;
TC1_q_b[6]_PORT_B_read_enable_reg = DFFE(TC1_q_b[6]_PORT_B_read_enable, TC1_q_b[6]_clock_0, , , );
TC1_q_b[6]_clock_0 = PCLK;
TC1_q_b[6]_PORT_B_data_out = MEMORY(TC1_q_b[6]_PORT_A_data_in_reg, , TC1_q_b[6]_PORT_A_address_reg, TC1_q_b[6]_PORT_B_address_reg, TC1_q_b[6]_PORT_A_write_enable_reg, TC1_q_b[6]_PORT_B_read_enable_reg, , , TC1_q_b[6]_clock_0, , , , , );
TC1_q_b[6]_PORT_B_data_out_reg = DFFE(TC1_q_b[6]_PORT_B_data_out, TC1_q_b[6]_clock_0, , , );
TC1_q_b[6] = TC1_q_b[6]_PORT_B_data_out_reg[0];


--SB1L04 is mesure_card_top:inst5|sender_video:sender_video0|pixel[1]~70
--operation mode is normal

SB1L04 = SB1_blank_dly36 & SB1_pixel_out[1] # !SB1_blank_dly36 & (TC1_q_b[6]);


--SB1_pixel_out[0] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[0]
--operation mode is normal

SB1_pixel_out[0]_lut_out = YB1_q_b[0];
SB1_pixel_out[0] = DFFEAS(SB1_pixel_out[0]_lut_out, PCLK, VCC, , , , , , );


--TC1_q_b[7] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 33, Port A Width: 1, Port B Depth: 33, Port B Width: 1
--Port A Logical Depth: 33, Port A Logical Width: 8, Port B Logical Depth: 33, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
TC1_q_b[7]_PORT_A_data_in = SB1_qd_reg_dly1[0];
TC1_q_b[7]_PORT_A_data_in_reg = DFFE(TC1_q_b[7]_PORT_A_data_in, TC1_q_b[7]_clock_0, , , );
TC1_q_b[7]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[7]_PORT_A_address_reg = DFFE(TC1_q_b[7]_PORT_A_address, TC1_q_b[7]_clock_0, , , );
TC1_q_b[7]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[7]_PORT_B_address_reg = DFFE(TC1_q_b[7]_PORT_B_address, TC1_q_b[7]_clock_0, , , );
TC1_q_b[7]_PORT_A_write_enable = VCC;
TC1_q_b[7]_PORT_A_write_enable_reg = DFFE(TC1_q_b[7]_PORT_A_write_enable, TC1_q_b[7]_clock_0, , , );
TC1_q_b[7]_PORT_B_read_enable = VCC;
TC1_q_b[7]_PORT_B_read_enable_reg = DFFE(TC1_q_b[7]_PORT_B_read_enable, TC1_q_b[7]_clock_0, , , );
TC1_q_b[7]_clock_0 = PCLK;
TC1_q_b[7]_PORT_B_data_out = MEMORY(TC1_q_b[7]_PORT_A_data_in_reg, , TC1_q_b[7]_PORT_A_address_reg, TC1_q_b[7]_PORT_B_address_reg, TC1_q_b[7]_PORT_A_write_enable_reg, TC1_q_b[7]_PORT_B_read_enable_reg, , , TC1_q_b[7]_clock_0, , , , , );
TC1_q_b[7]_PORT_B_data_out_reg = DFFE(TC1_q_b[7]_PORT_B_data_out, TC1_q_b[7]_clock_0, , , );
TC1_q_b[7] = TC1_q_b[7]_PORT_B_data_out_reg[0];


--SB1L93 is mesure_card_top:inst5|sender_video:sender_video0|pixel[0]~71
--operation mode is normal

SB1L93 = SB1_blank_dly36 & SB1_pixel_out[0] # !SB1_blank_dly36 & (TC1_q_b[7]);


--N1_led[3] is Led_run:inst21|led[3]
--operation mode is normal

N1_led[3]_lut_out = N1_led[2] & (!N1_dir);
N1_led[3] = DFFEAS(N1_led[3]_lut_out, N1_Mega_cnt[23], RST, , , , , , );


--N1_led[2] is Led_run:inst21|led[2]
--operation mode is normal

N1_led[2]_lut_out = N1_dir & N1_led[3] # !N1_dir & (!N1_led[1]);
N1_led[2] = DFFEAS(N1_led[2]_lut_out, N1_Mega_cnt[23], RST, , , , , , );


--N1_led[1] is Led_run:inst21|led[1]
--operation mode is normal

N1_led[1]_lut_out = N1_dir & !N1_led[2] # !N1_dir & (!N1_led[0]);
N1_led[1] = DFFEAS(N1_led[1]_lut_out, N1_Mega_cnt[23], RST, , , , , , );


--N1_led[0] is Led_run:inst21|led[0]
--operation mode is normal

N1_led[0]_lut_out = N1_dir & (!N1_led[1]);
N1_led[0] = DFFEAS(N1_led[0]_lut_out, N1_Mega_cnt[23], RST, , , , , , );


--PB1_SA[10] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[10]
--operation mode is normal

PB1_SA[10]_lut_out = DC1_SA[10];
PB1_SA[10] = DFFEAS(PB1_SA[10]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_SA[9] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[9]
--operation mode is normal

PB1_SA[9]_lut_out = DC1_SA[9];
PB1_SA[9] = DFFEAS(PB1_SA[9]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_SA[8] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[8]
--operation mode is normal

PB1_SA[8]_lut_out = DC1_SA[8];
PB1_SA[8] = DFFEAS(PB1_SA[8]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_SA[7] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[7]
--operation mode is normal

PB1_SA[7]_lut_out = DC1_SA[7];
PB1_SA[7] = DFFEAS(PB1_SA[7]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_SA[6] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[6]
--operation mode is normal

PB1_SA[6]_lut_out = DC1_SA[6];
PB1_SA[6] = DFFEAS(PB1_SA[6]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_SA[5] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[5]
--operation mode is normal

PB1_SA[5]_lut_out = DC1_SA[5];
PB1_SA[5] = DFFEAS(PB1_SA[5]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_SA[4] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[4]
--operation mode is normal

PB1_SA[4]_lut_out = DC1_SA[4];
PB1_SA[4] = DFFEAS(PB1_SA[4]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_SA[3] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[3]
--operation mode is normal

PB1_SA[3]_lut_out = DC1_SA[3];
PB1_SA[3] = DFFEAS(PB1_SA[3]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_SA[2] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[2]
--operation mode is normal

PB1_SA[2]_lut_out = DC1_SA[2];
PB1_SA[2] = DFFEAS(PB1_SA[2]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_SA[1] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[1]
--operation mode is normal

PB1_SA[1]_lut_out = DC1_SA[1];
PB1_SA[1] = DFFEAS(PB1_SA[1]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_SA[0] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|SA[0]
--operation mode is normal

PB1_SA[0]_lut_out = DC1_SA[0];
PB1_SA[0] = DFFEAS(PB1_SA[0]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_BA[1] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|BA[1]
--operation mode is normal

PB1_BA[1]_lut_out = DC1_BA[1];
PB1_BA[1] = DFFEAS(PB1_BA[1]_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_BA[0] is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|BA[0]
--operation mode is normal

PB1_BA[0]_lut_out = DC1_BA[0];
PB1_BA[0] = DFFEAS(PB1_BA[0]_lut_out, Z1__clk0, VCC, , , , , , );


--DC1_CAS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|CAS_N
--operation mode is normal

DC1_CAS_N_lut_out = !DC1_do_refresh & (DC1L5 # DC1L63);
DC1_CAS_N = DFFEAS(DC1_CAS_N_lut_out, Z1__clk0, VCC, , , VCC, , , !RST);


--DC1_CS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|CS_N
--operation mode is normal

DC1_CS_N_lut_out = !RST;
DC1_CS_N = DFFEAS(DC1_CS_N_lut_out, Z1__clk0, VCC, , , , , , );


--DC1_RAS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|RAS_N
--operation mode is normal

DC1_RAS_N_lut_out = !DC1_do_refresh & (DC1L63 # !DC1L11);
DC1_RAS_N = DFFEAS(DC1_RAS_N_lut_out, Z1__clk0, VCC, , , VCC, , , !RST);


--DC1_WE_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|command:command1|WE_N
--operation mode is normal

DC1_WE_N_lut_out = DC1_do_refresh # DC1L82 & !DC1L63;
DC1_WE_N = DFFEAS(DC1_WE_N_lut_out, Z1__clk0, VCC, , , VCC, , , !RST);


--YB1_q_b[7] is mesure_card_top:inst5|ram256_32to1k_8:ram_s0|altsyncram:altsyncram_component|altsyncram_m951:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 256, Port A Width: 4, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
YB1_q_b[7]_PORT_A_data_in = BUS(CB1_s_ram_wdb[7], CB1_s_ram_wdb[15], CB1_s_ram_wdb[23], CB1_s_ram_wdb[31]);
YB1_q_b[7]_PORT_A_data_in_reg = DFFE(YB1_q_b[7]_PORT_A_data_in, YB1_q_b[7]_clock_0, , , YB1_q_b[7]_clock_enable_0);
YB1_q_b[7]_PORT_A_address = BUS(CB1_s_ram_wab_reg[0], CB1_s_ram_wab_reg[1], CB1_s_ram_wab_reg[2], CB1_s_ram_wab_reg[3], CB1_s_ram_wab_reg[4], CB1_s_ram_wab_reg[5], CB1_s_ram_wab_reg[6], CB1_s_ram_wab_reg[7]);
YB1_q_b[7]_PORT_A_address_reg = DFFE(YB1_q_b[7]_PORT_A_address, YB1_q_b[7]_clock_0, , , YB1_q_b[7]_clock_enable_0);
YB1_q_b[7]_PORT_B_address = BUS(SB1_send_ram_rab_reg[0], SB1_send_ram_rab_reg[1], SB1_send_ram_rab_reg[2], SB1_send_ram_rab_reg[3], SB1_send_ram_rab_reg[4], SB1_send_ram_rab_reg[5], SB1_send_ram_rab_reg[6], SB1_send_ram_rab_reg[7], SB1_send_ram_rab_reg[8], SB1_send_ram_rab_reg[9]);
YB1_q_b[7]_PORT_B_address_reg = DFFE(YB1_q_b[7]_PORT_B_address, YB1_q_b[7]_clock_1, , , );
YB1_q_b[7]_PORT_A_write_enable = VCC;
YB1_q_b[7]_PORT_A_write_enable_reg = DFFE(YB1_q_b[7]_PORT_A_write_enable, YB1_q_b[7]_clock_0, , , YB1_q_b[7]_clock_enable_0);
YB1_q_b[7]_PORT_B_read_enable = VCC;
YB1_q_b[7]_PORT_B_read_enable_reg = DFFE(YB1_q_b[7]_PORT_B_read_enable, YB1_q_b[7]_clock_1, , , );
YB1_q_b[7]_clock_0 = Z1__clk0;
YB1_q_b[7]_clock_1 = PCLK;
YB1_q_b[7]_clock_enable_0 = CB1_s_enable;
YB1_q_b[7]_PORT_B_data_out = MEMORY(YB1_q_b[7]_PORT_A_data_in_reg, , YB1_q_b[7]_PORT_A_address_reg, YB1_q_b[7]_PORT_B_address_reg, YB1_q_b[7]_PORT_A_write_enable_reg, YB1_q_b[7]_PORT_B_read_enable_reg, , , YB1_q_b[7]_clock_0, YB1_q_b[7]_clock_1, YB1_q_b[7]_clock_enable_0, , , );
YB1_q_b[7] = YB1_q_b[7]_PORT_B_data_out[0];


--SB1_qd_reg_dly1[7] is mesure_card_top:inst5|sender_video:sender_video0|qd_reg_dly1[7]
--operation mode is normal

SB1_qd_reg_dly1[7]_lut_out = H1L55Q & H1_qd_dly[7] # !H1L55Q & (H1L45Q & H1_qd_dly[7] # !H1L45Q & (H1_qd_dly1[7]));
SB1_qd_reg_dly1[7] = DFFEAS(SB1_qd_reg_dly1[7]_lut_out, PCLK, VCC, , , , , , );