i2c_altera.map.eqn

视频采集

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--Z1__clk0 is PLL:inst3|altpll:altpll_component|_clk0
Z1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(SYSCLK), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--Z1__clk1 is PLL:inst3|altpll:altpll_component|_clk1
Z1__clk1 = PLL.CLK1(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(SYSCLK), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--PB1_CAS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|CAS_N
--operation mode is normal

PB1_CAS_N_lut_out = DC1_CAS_N;
PB1_CAS_N = DFFEAS(PB1_CAS_N_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_CS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|CS_N
--operation mode is normal

PB1_CS_N_lut_out = DC1_CS_N;
PB1_CS_N = DFFEAS(PB1_CS_N_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_RAS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|RAS_N
--operation mode is normal

PB1_RAS_N_lut_out = DC1_RAS_N;
PB1_RAS_N = DFFEAS(PB1_RAS_N_lut_out, Z1__clk0, VCC, , , , , , );


--PB1_WE_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|WE_N
--operation mode is normal

PB1_WE_N_lut_out = DC1_WE_N;
PB1_WE_N = DFFEAS(PB1_WE_N_lut_out, Z1__clk0, VCC, , , , , , );


--SB1_pixel_out[7] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[7]
--operation mode is normal

SB1_pixel_out[7]_lut_out = YB1_q_b[7];
SB1_pixel_out[7] = DFFEAS(SB1_pixel_out[7]_lut_out, PCLK, VCC, , , , , , );


--TC1_q_b[0] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 33, Port A Width: 1, Port B Depth: 33, Port B Width: 1
--Port A Logical Depth: 33, Port A Logical Width: 8, Port B Logical Depth: 33, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
TC1_q_b[0]_PORT_A_data_in = SB1_qd_reg_dly1[7];
TC1_q_b[0]_PORT_A_data_in_reg = DFFE(TC1_q_b[0]_PORT_A_data_in, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_A_address_reg = DFFE(TC1_q_b[0]_PORT_A_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_B_address_reg = DFFE(TC1_q_b[0]_PORT_B_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_write_enable = VCC;
TC1_q_b[0]_PORT_A_write_enable_reg = DFFE(TC1_q_b[0]_PORT_A_write_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_read_enable = VCC;
TC1_q_b[0]_PORT_B_read_enable_reg = DFFE(TC1_q_b[0]_PORT_B_read_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_clock_0 = PCLK;
TC1_q_b[0]_PORT_B_data_out = MEMORY(TC1_q_b[0]_PORT_A_data_in_reg, , TC1_q_b[0]_PORT_A_address_reg, TC1_q_b[0]_PORT_B_address_reg, TC1_q_b[0]_PORT_A_write_enable_reg, TC1_q_b[0]_PORT_B_read_enable_reg, , , TC1_q_b[0]_clock_0, , , , , );
TC1_q_b[0]_PORT_B_data_out_reg = DFFE(TC1_q_b[0]_PORT_B_data_out, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0] = TC1_q_b[0]_PORT_B_data_out_reg[0];


--SB1_blank_dly36 is mesure_card_top:inst5|sender_video:sender_video0|blank_dly36
--operation mode is normal

SB1_blank_dly36_lut_out = SB1_blank_dly35;
SB1_blank_dly36 = DFFEAS(SB1_blank_dly36_lut_out, PCLK, VCC, , , , , , );


--SB1L64 is mesure_card_top:inst5|sender_video:sender_video0|pixel[7]~64
--operation mode is normal

SB1L64 = SB1_blank_dly36 & SB1_pixel_out[7] # !SB1_blank_dly36 & (TC1_q_b[0]);


--SB1_pixel_out[6] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[6]
--operation mode is normal

SB1_pixel_out[6]_lut_out = YB1_q_b[6];
SB1_pixel_out[6] = DFFEAS(SB1_pixel_out[6]_lut_out, PCLK, VCC, , , , , , );


--TC1_q_b[1] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 33, Port A Width: 1, Port B Depth: 33, Port B Width: 1
--Port A Logical Depth: 33, Port A Logical Width: 8, Port B Logical Depth: 33, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
TC1_q_b[1]_PORT_A_data_in = SB1_qd_reg_dly1[6];
TC1_q_b[1]_PORT_A_data_in_reg = DFFE(TC1_q_b[1]_PORT_A_data_in, TC1_q_b[1]_clock_0, , , );
TC1_q_b[1]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[1]_PORT_A_address_reg = DFFE(TC1_q_b[1]_PORT_A_address, TC1_q_b[1]_clock_0, , , );
TC1_q_b[1]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[1]_PORT_B_address_reg = DFFE(TC1_q_b[1]_PORT_B_address, TC1_q_b[1]_clock_0, , , );
TC1_q_b[1]_PORT_A_write_enable = VCC;
TC1_q_b[1]_PORT_A_write_enable_reg = DFFE(TC1_q_b[1]_PORT_A_write_enable, TC1_q_b[1]_clock_0, , , );
TC1_q_b[1]_PORT_B_read_enable = VCC;
TC1_q_b[1]_PORT_B_read_enable_reg = DFFE(TC1_q_b[1]_PORT_B_read_enable, TC1_q_b[1]_clock_0, , , );
TC1_q_b[1]_clock_0 = PCLK;
TC1_q_b[1]_PORT_B_data_out = MEMORY(TC1_q_b[1]_PORT_A_data_in_reg, , TC1_q_b[1]_PORT_A_address_reg, TC1_q_b[1]_PORT_B_address_reg, TC1_q_b[1]_PORT_A_write_enable_reg, TC1_q_b[1]_PORT_B_read_enable_reg, , , TC1_q_b[1]_clock_0, , , , , );
TC1_q_b[1]_PORT_B_data_out_reg = DFFE(TC1_q_b[1]_PORT_B_data_out, TC1_q_b[1]_clock_0, , , );
TC1_q_b[1] = TC1_q_b[1]_PORT_B_data_out_reg[0];


--SB1L54 is mesure_card_top:inst5|sender_video:sender_video0|pixel[6]~65
--operation mode is normal

SB1L54 = SB1_blank_dly36 & SB1_pixel_out[6] # !SB1_blank_dly36 & (TC1_q_b[1]);


--SB1_pixel_out[5] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[5]
--operation mode is normal

SB1_pixel_out[5]_lut_out = YB1_q_b[5];
SB1_pixel_out[5] = DFFEAS(SB1_pixel_out[5]_lut_out, PCLK, VCC, , , , , , );


--TC1_q_b[2] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 33, Port A Width: 1, Port B Depth: 33, Port B Width: 1
--Port A Logical Depth: 33, Port A Logical Width: 8, Port B Logical Depth: 33, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
TC1_q_b[2]_PORT_A_data_in = SB1_qd_reg_dly1[5];
TC1_q_b[2]_PORT_A_data_in_reg = DFFE(TC1_q_b[2]_PORT_A_data_in, TC1_q_b[2]_clock_0, , , );
TC1_q_b[2]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[2]_PORT_A_address_reg = DFFE(TC1_q_b[2]_PORT_A_address, TC1_q_b[2]_clock_0, , , );
TC1_q_b[2]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[2]_PORT_B_address_reg = DFFE(TC1_q_b[2]_PORT_B_address, TC1_q_b[2]_clock_0, , , );
TC1_q_b[2]_PORT_A_write_enable = VCC;
TC1_q_b[2]_PORT_A_write_enable_reg = DFFE(TC1_q_b[2]_PORT_A_write_enable, TC1_q_b[2]_clock_0, , , );
TC1_q_b[2]_PORT_B_read_enable = VCC;
TC1_q_b[2]_PORT_B_read_enable_reg = DFFE(TC1_q_b[2]_PORT_B_read_enable, TC1_q_b[2]_clock_0, , , );
TC1_q_b[2]_clock_0 = PCLK;
TC1_q_b[2]_PORT_B_data_out = MEMORY(TC1_q_b[2]_PORT_A_data_in_reg, , TC1_q_b[2]_PORT_A_address_reg, TC1_q_b[2]_PORT_B_address_reg, TC1_q_b[2]_PORT_A_write_enable_reg, TC1_q_b[2]_PORT_B_read_enable_reg, , , TC1_q_b[2]_clock_0, , , , , );
TC1_q_b[2]_PORT_B_data_out_reg = DFFE(TC1_q_b[2]_PORT_B_data_out, TC1_q_b[2]_clock_0, , , );
TC1_q_b[2] = TC1_q_b[2]_PORT_B_data_out_reg[0];


--SB1L44 is mesure_card_top:inst5|sender_video:sender_video0|pixel[5]~66
--operation mode is normal

SB1L44 = SB1_blank_dly36 & SB1_pixel_out[5] # !SB1_blank_dly36 & (TC1_q_b[2]);


--SB1_pixel_out[4] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[4]
--operation mode is normal

SB1_pixel_out[4]_lut_out = YB1_q_b[4];
SB1_pixel_out[4] = DFFEAS(SB1_pixel_out[4]_lut_out, PCLK, VCC, , , , , , );


--TC1_q_b[3] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 33, Port A Width: 1, Port B Depth: 33, Port B Width: 1
--Port A Logical Depth: 33, Port A Logical Width: 8, Port B Logical Depth: 33, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
TC1_q_b[3]_PORT_A_data_in = SB1_qd_reg_dly1[4];
TC1_q_b[3]_PORT_A_data_in_reg = DFFE(TC1_q_b[3]_PORT_A_data_in, TC1_q_b[3]_clock_0, , , );
TC1_q_b[3]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[3]_PORT_A_address_reg = DFFE(TC1_q_b[3]_PORT_A_address, TC1_q_b[3]_clock_0, , , );
TC1_q_b[3]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[3]_PORT_B_address_reg = DFFE(TC1_q_b[3]_PORT_B_address, TC1_q_b[3]_clock_0, , , );
TC1_q_b[3]_PORT_A_write_enable = VCC;
TC1_q_b[3]_PORT_A_write_enable_reg = DFFE(TC1_q_b[3]_PORT_A_write_enable, TC1_q_b[3]_clock_0, , , );
TC1_q_b[3]_PORT_B_read_enable = VCC;
TC1_q_b[3]_PORT_B_read_enable_reg = DFFE(TC1_q_b[3]_PORT_B_read_enable, TC1_q_b[3]_clock_0, , , );
TC1_q_b[3]_clock_0 = PCLK;
TC1_q_b[3]_PORT_B_data_out = MEMORY(TC1_q_b[3]_PORT_A_data_in_reg, , TC1_q_b[3]_PORT_A_address_reg, TC1_q_b[3]_PORT_B_address_reg, TC1_q_b[3]_PORT_A_write_enable_reg, TC1_q_b[3]_PORT_B_read_enable_reg, , , TC1_q_b[3]_clock_0, , , , , );
TC1_q_b[3]_PORT_B_data_out_reg = DFFE(TC1_q_b[3]_PORT_B_data_out, TC1_q_b[3]_clock_0, , , );
TC1_q_b[3] = TC1_q_b[3]_PORT_B_data_out_reg[0];


--SB1L34 is mesure_card_top:inst5|sender_video:sender_video0|pixel[4]~67
--operation mode is normal

SB1L34 = SB1_blank_dly36 & SB1_pixel_out[4] # !SB1_blank_dly36 & (TC1_q_b[3]);


--SB1_pixel_out[3] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[3]
--operation mode is normal

SB1_pixel_out[3]_lut_out = YB1_q_b[3];
SB1_pixel_out[3] = DFFEAS(SB1_pixel_out[3]_lut_out, PCLK, VCC, , , , , , );


--TC1_q_b[4] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 33, Port A Width: 1, Port B Depth: 33, Port B Width: 1
--Port A Logical Depth: 33, Port A Logical Width: 8, Port B Logical Depth: 33, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
TC1_q_b[4]_PORT_A_data_in = SB1_qd_reg_dly1[3];
TC1_q_b[4]_PORT_A_data_in_reg = DFFE(TC1_q_b[4]_PORT_A_data_in, TC1_q_b[4]_clock_0, , , );
TC1_q_b[4]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[4]_PORT_A_address_reg = DFFE(TC1_q_b[4]_PORT_A_address, TC1_q_b[4]_clock_0, , , );
TC1_q_b[4]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[4]_PORT_B_address_reg = DFFE(TC1_q_b[4]_PORT_B_address, TC1_q_b[4]_clock_0, , , );
TC1_q_b[4]_PORT_A_write_enable = VCC;
TC1_q_b[4]_PORT_A_write_enable_reg = DFFE(TC1_q_b[4]_PORT_A_write_enable, TC1_q_b[4]_clock_0, , , );
TC1_q_b[4]_PORT_B_read_enable = VCC;
TC1_q_b[4]_PORT_B_read_enable_reg = DFFE(TC1_q_b[4]_PORT_B_read_enable, TC1_q_b[4]_clock_0, , , );
TC1_q_b[4]_clock_0 = PCLK;
TC1_q_b[4]_PORT_B_data_out = MEMORY(TC1_q_b[4]_PORT_A_data_in_reg, , TC1_q_b[4]_PORT_A_address_reg, TC1_q_b[4]_PORT_B_address_reg, TC1_q_b[4]_PORT_A_write_enable_reg, TC1_q_b[4]_PORT_B_read_enable_reg, , , TC1_q_b[4]_clock_0, , , , , );
TC1_q_b[4]_PORT_B_data_out_reg = DFFE(TC1_q_b[4]_PORT_B_data_out, TC1_q_b[4]_clock_0, , , );
TC1_q_b[4] = TC1_q_b[4]_PORT_B_data_out_reg[0];


--SB1L24 is mesure_card_top:inst5|sender_video:sender_video0|pixel[3]~68
--operation mode is normal

SB1L24 = SB1_blank_dly36 & SB1_pixel_out[3] # !SB1_blank_dly36 & (TC1_q_b[4]);


--SB1_pixel_out[2] is mesure_card_top:inst5|sender_video:sender_video0|pixel_out[2]
--operation mode is normal

SB1_pixel_out[2]_lut_out = YB1_q_b[2];
SB1_pixel_out[2] = DFFEAS(SB1_pixel_out[2]_lut_out, PCLK, VCC, , , , , , );


--TC1_q_b[5] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 33, Port A Width: 1, Port B Depth: 33, Port B Width: 1
--Port A Logical Depth: 33, Port A Logical Width: 8, Port B Logical Depth: 33, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
TC1_q_b[5]_PORT_A_data_in = SB1_qd_reg_dly1[2];
TC1_q_b[5]_PORT_A_data_in_reg = DFFE(TC1_q_b[5]_PORT_A_data_in, TC1_q_b[5]_clock_0, , , );
TC1_q_b[5]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[5]_PORT_A_address_reg = DFFE(TC1_q_b[5]_PORT_A_address, TC1_q_b[5]_clock_0, , , );
TC1_q_b[5]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[5]_PORT_B_address_reg = DFFE(TC1_q_b[5]_PORT_B_address, TC1_q_b[5]_clock_0, , , );
TC1_q_b[5]_PORT_A_write_enable = VCC;
TC1_q_b[5]_PORT_A_write_enable_reg = DFFE(TC1_q_b[5]_PORT_A_write_enable, TC1_q_b[5]_clock_0, , , );
TC1_q_b[5]_PORT_B_read_enable = VCC;
TC1_q_b[5]_PORT_B_read_enable_reg = DFFE(TC1_q_b[5]_PORT_B_read_enable, TC1_q_b[5]_clock_0, , , );
TC1_q_b[5]_clock_0 = PCLK;
TC1_q_b[5]_PORT_B_data_out = MEMORY(TC1_q_b[5]_PORT_A_data_in_reg, , TC1_q_b[5]_PORT_A_address_reg, TC1_q_b[5]_PORT_B_address_reg, TC1_q_b[5]_PORT_A_write_enable_reg, TC1_q_b[5]_PORT_B_read_enable_reg, , , TC1_q_b[5]_clock_0, , , , , );
TC1_q_b[5]_PORT_B_data_out_reg = DFFE(TC1_q_b[5]_PORT_B_data_out, TC1_q_b[5]_clock_0, , , );
TC1_q_b[5] = TC1_q_b[5]_PORT_B_data_out_reg[0];