datacnl.v

视频采集

module datacnl(	
	clk,
	rst,

	r_ram_rdb,	
	r_ram_rab,	
	r_req_in,
	r_ack,
	r_busy,
	
	s_ram_wdb,
	s_ram_wab,
	s_ram_wab_video,
	s_ram_wen,	
	s_req_in,
	s_ack,
	
	cmd,
	cmdack,
	addr,
	datain,
	dataout,

	start_send,
	start_read,
	mode_vga_in,
				
	vsync,
	vsync_vga,
	r_ba0
                );

//--------------------ports--------------------
input	clk,rst;
input	[31:0]	r_ram_rdb;
input	cmdack;
input	[31:0]	dataout;
input	r_req_in,s_req_in;
input	start_read,mode_vga_in,vsync;
input	vsync_vga;
input	r_busy;

output	r_ack;
output	[7:0]	r_ram_rab;
output	s_ram_wen;
output	[8:0]	s_ram_wab;
output [7:0] s_ram_wab_video;
output	[2:0]	cmd;
output	[20:0]	addr;
output	[31:0]	datain,s_ram_wdb;

output	start_send;
output	s_ack;
output	r_ba0;
//---------port variables declaration-----------
wire	clk,rst;
wire	cmdack;
wire	[31:0]	dataout;
wire	r_req_in,s_req_in;
reg	[2:0]	cmd;
reg	[20:0]	addr;
reg	[31:0]	s_ram_wdb;
wire	[31:0]	datain;
wire	s_ram_wen;
reg	start_send;

// State parameters used in MAIN  STATE MACHINE
parameter 
	IDLE		=21'b0_0000_0000_0000_0000_0001,
	PRECHARGE	=21'b0_0000_0000_0000_0000_0010,
	PRECHARGE_ACK	=21'b0_0000_0000_0000_0000_0100,    
	LOAD_MR		=21'b0_0000_0000_0000_0000_1000,
	LOAD_MR_ACK	=21'b0_0000_0000_0000_0001_0000,
	LOAD_R2		=21'b0_0000_0000_0000_0010_0000,
	LOAD_R2_ACK	=21'b0_0000_0000_0000_0100_0000,
	LOAD_R1		=21'b0_0000_0000_0000_1000_0000,
                          
	IDLE_WR		=21'b0_0000_0000_0001_0000_0000,    
	PAGE_WRITE	=21'b0_0000_0000_0010_0000_0000,
	BURST_WRITE	=21'b0_0000_0000_0100_0000_0000,
	BT_W		=21'b0_0000_0000_1000_0000_0000,
	WAIT_ACK_W_T	=21'b0_0000_0001_0000_0000_0000,
                         
	PAGE_READ	=21'b0_0000_0010_0000_0000_0000,
	BURST_READ	=21'b0_0000_0100_0000_0000_0000,
	BT		=21'b0_0000_1000_0000_0000_0000,
	LAST_DATA	=21'b0_0001_0000_0000_0000_0000,
	CLOSE_PAGE_W	=21'b0_0010_0000_0000_0000_0000,
	REFRESH_W       =21'b0_0100_0000_0000_0000_0000,
	CLOSE_PAGE_R    =21'b0_1000_0000_0000_0000_0000,
	REFRESH_R       =21'b1_0000_0000_0000_0000_0000;
	
parameter RCD='D3,CL='D3,BL='d180;//H_PIXELS>>2;

reg	s_enable;
reg	[20:0]	STATE;
reg	[10:0]	w_page;
reg	[1:0]	w_ba;
reg	[7:0]	Burst_cnt;
reg	[1:0]	RCDCL_CNT;
reg	[8*10:0]	cmd_name;
reg	[8*12:0]	state_name;
//reg	send_cnl;

reg	s_req,r_req,mode_vga,s_req1,r_req1;
reg	vsync_reg,vsync_vga_reg,vsync_reg1,vsync_vga_reg1;

always @ (posedge clk)
begin
	s_req1 <= s_req_in;
	s_req <= s_req1;
	r_req1 <= r_req_in;
	r_req <= r_req1;
	mode_vga <= mode_vga_in;
	vsync_reg <= vsync_reg1;
	vsync_reg1 <= vsync;
	vsync_vga_reg1 <= vsync_vga;
	vsync_vga_reg <= vsync_vga_reg1;
end

always @ cmd
case (cmd)
  'b000: cmd_name="NOP";
  'b001: cmd_name="READA";
  'b010: cmd_name="WRITEA";
  'b011: cmd_name="REFRESH";
  'b100: cmd_name="PRECHARGE";
  'b101: cmd_name="LOAD_MODE";
  'b110: cmd_name="LOAD_REG1";
  'b111: cmd_name="LOAD_REG2";
  endcase
  
always @ STATE
case(STATE)
 	PRECHARGE:	state_name="PRECHARGE";
	PRECHARGE_ACK:	state_name="PRECHARGE_ACK";
	LOAD_MR:	state_name="LOAD_MR";
	LOAD_MR_ACK:	state_name="LOAD_MR_ACK";
	LOAD_R2:	state_name="LOAD_R2";
	LOAD_R2_ACK:	state_name="LOAD_R2_ACK";
	LOAD_R1:	state_name="LOAD_R1";
	IDLE_WR:	state_name="IDLE_WR";
 	PAGE_WRITE:	state_name="PAGE_WRITE";
	BURST_WRITE:	state_name="BURST_WRITE";
	BT_W:		state_name="BT_W";
	CLOSE_PAGE_W:	state_name="CLOSE_PAGE_W";
	CLOSE_PAGE_R:	state_name="CLOSE_PAGE_R";
	PAGE_READ:	state_name="PAGE_READ";
	BURST_READ:	state_name="BURST_READ";
	BT:		state_name="BT";
	LAST_DATA:	state_name="LAST_DATA";
	REFRESH_R:	state_name="REFRESH_R";
	REFRESH_W:	state_name="REFRESH_W";
	default:	state_name="default";
	endcase
 


//transfer the data bus
always @ (posedge clk) begin	
	s_ram_wdb <= dataout;
	end
assign	datain = r_ram_rdb;

reg	[7:0]	r_ram_rab;
reg	STATE12_reg,STATE16_reg,STATE8_reg,STATE19_reg;

always @ (posedge clk) begin
	STATE12_reg <= STATE[12];
	STATE16_reg <= STATE[16];
	STATE8_reg  <= STATE[8];
	STATE19_reg <= STATE[19];
end

always @ (posedge clk or negedge rst)
if(!rst)
	r_ram_rab <= 0;
else if((STATE[9]&cmdack)|STATE[10])
	r_ram_rab <= r_ram_rab + 1;
else if(STATE12_reg)
	r_ram_rab<=0;
	    
//generate the write address bus data
reg	[7:0]	s_ram_wab_reg;
reg	s_ram_wab_hbit;
wire	[8:0]	s_ram_wab = {s_ram_wab_hbit,s_ram_wab_reg};
wire	[7:0]	s_ram_wab_video =s_ram_wab_reg;   
always @ (posedge clk or negedge rst)
if(!rst) begin
	s_ram_wab_reg<='d0;
	end
else  begin
	if(s_enable)
		s_ram_wab_reg<=s_ram_wab_reg+1;
	else
		s_ram_wab_reg<=0;
	end

	
always @ (posedge clk or negedge rst)
if(!rst) begin
	s_ram_wab_hbit<=0;
	end
else  begin
	if(STATE19_reg & cmdack)
		s_ram_wab_hbit <= ~s_ram_wab_hbit;
	if(mode_vga) begin
		if(!vsync_vga_reg)
			s_ram_wab_hbit <= 0;
		end
	else begin
		if(!vsync_reg)
			s_ram_wab_hbit <= 0;
		end
	end


always @ (posedge clk or negedge rst)
if(!rst)
	start_send <= 0;
else if(((w_ba[0] & w_page == 'd480) & mode_vga) | w_ba[1])
	start_send <= 1;
	
//generate the send wen signal 
assign s_ram_wen = s_enable;



parameter	NOP       ='b000,
		READA     ='b001,
		WRITEA    ='b010,
		ARF       ='b011,
		PRECHRG   ='b100,
		LOAD_MODE ='b101,
		LOAD_REG1 ='b110,
		LOAD_REG2 ='b111;
		
//generate the cmd to the sdr_sdram_controller
always @ (STATE)
case(STATE)    
	PRECHARGE:	cmd = PRECHRG;
	LOAD_MR:	cmd = LOAD_MODE;
	LOAD_R2:	cmd = LOAD_REG2;
	LOAD_R1:	cmd = LOAD_REG1;
	PAGE_WRITE:	cmd = WRITEA;
	BT_W:		cmd = PRECHRG;
	CLOSE_PAGE_W:	cmd = PRECHRG;
	CLOSE_PAGE_R:	cmd = PRECHRG;
	PAGE_READ:	cmd = READA;
	BT:		cmd = PRECHRG;
	REFRESH_W:	cmd = ARF;
	REFRESH_R:	cmd = ARF;
	default:	cmd = NOP;
endcase
//*****************************************************************************//
//*****************************************************************************//
always @ (posedge clk or negedge rst)
if(!rst)
	w_page <= 0;
else if(STATE12_reg)
	w_page <= w_page + 1;
else if(STATE8_reg&(!vsync_reg))
	w_page <= 0;

always @ (posedge clk or negedge rst)
if(!rst)
	w_ba <= 0;
else if(STATE8_reg&(!vsync_reg)) begin
	if(w_page!=0)
		w_ba <= w_ba + 1;
	end
//****************************************************************************//
//****************************************************************************//
reg	[10:0]	r_page_video;
reg	[1:0]	r_ba_video;


always @ (posedge clk or negedge rst)
if(!rst) 
	r_page_video <= 0;
else if(!mode_vga) begin
	if(STATE16_reg)
		r_page_video <= r_page_video + 1;
	else if(!vsync_reg1 & (vsync_reg))
		r_page_video <= 0;
	end


always @ (posedge clk or negedge rst)
if(!rst)
	r_ba_video <= 0;
else if(!mode_vga) begin
	if(!vsync_reg1 & (vsync_reg)) begin
			r_ba_video<=w_ba + 2'd3;
		end
	end	


reg	r_ba0_vga,r_ba1_vga,ba0_cnl;
always @ (posedge clk or negedge rst)
if(!rst) begin
	r_ba0_vga <= 1;
	ba0_cnl <= 0;
	end
else if(mode_vga) begin
	if(STATE[20] & cmdack) begin
		ba0_cnl <= ~ba0_cnl;
		if(ba0_cnl)
			r_ba0_vga <= ~r_ba0_vga;
		end	
	else if(!vsync_vga_reg) begin
		r_ba0_vga <= 1;
		ba0_cnl <= 0;
		end
	end

always @ (posedge clk or negedge rst)
if(!rst)
	r_ba1_vga <= 0;
else
	r_ba1_vga <= ~w_ba[1];

	
wire	[1:0]	r_ba_vga = {r_ba1_vga,r_ba0_vga};
wire	[1:0]	r_ba = mode_vga ? r_ba_vga : r_ba_video;
reg		r_ba0;
always @ (posedge clk)
r_ba0 <= r_ba[0];
	
reg	[10:0]	r_page_vga_odd,r_page_vga_even;

always @ (posedge clk or negedge rst)
if(!rst) begin
	r_page_vga_odd <= 0;
	r_page_vga_even <= 0;
	end
else if(STATE16_reg & mode_vga) begin
	if(!r_ba0_vga)
		r_page_vga_odd <= r_page_vga_odd + 1;
	else
		r_page_vga_even <= r_page_vga_even + 1;
	end
else if(STATE8_reg & (!vsync_vga_reg)) begin
	r_page_vga_odd <= 0;
	r_page_vga_even <= 0;
	end
	
wire	[10:0]	r_page_vga = r_ba0_vga ? r_page_vga_even : r_page_vga_odd;
wire	[10:0]	r_page = mode_vga ? r_page_vga : r_page_video;

//********************************************************************************//
//********************************************************************************//				
//the state machine
always @(posedge clk or negedge rst)
begin
if(!rst) begin
        STATE<=IDLE;
	s_enable<=0;
//	send_cnl<=0;
        RCDCL_CNT<=0;
        Burst_cnt<=0;
	end
else
     case(STATE)
	IDLE:
	if(start_read)
		STATE<=PRECHARGE;
	else
		STATE<=IDLE;
		
	PRECHARGE:
	if(cmdack)
		STATE<=PRECHARGE_ACK;
	else
		STATE<=PRECHARGE;
		
	PRECHARGE_ACK:
		STATE<=LOAD_MR;
		
	LOAD_MR:
	if(cmdack)  
		STATE<=LOAD_MR_ACK;
	else
		STATE<=LOAD_MR;
		
	LOAD_MR_ACK:
		STATE<=LOAD_R2;
		
	LOAD_R2:
	if(cmdack)
 		STATE<=LOAD_R2_ACK;
	else
		STATE<=LOAD_R2;
		
	LOAD_R2_ACK:
		STATE<=LOAD_R1;
	LOAD_R1:
	if(cmdack)
		STATE<=IDLE_WR;
	else
		STATE<=LOAD_R1;

//page write burst
	IDLE_WR: begin                //9
	if(r_req) begin
		STATE<=PAGE_WRITE;
		end
	else if( s_req & !r_busy) begin
		STATE<=PAGE_READ;
		end  
	else
		STATE<=IDLE_WR;
	end
	
	PAGE_WRITE: //10
	if(cmdack) begin
		STATE<=BURST_WRITE; 
		Burst_cnt<=0;
		end
	else
		STATE<=PAGE_WRITE;  
		
	BURST_WRITE: begin
	if(Burst_cnt==(8'd177))//256-BL
		STATE<=BT_W;
	else
		STATE<=BURST_WRITE;
	Burst_cnt<=Burst_cnt+1;
	end  
	
	BT_W:begin          //12
	if(cmdack)
		STATE<=WAIT_ACK_W_T;
	else
		STATE<=BT_W;
	end

	WAIT_ACK_W_T:begin
	STATE<=CLOSE_PAGE_W;
	end        
	 
//CLOSE CURRENT PAGE                       
	CLOSE_PAGE_W:begin
	if(cmdack)
		STATE<=REFRESH_W;
	else
		STATE<=CLOSE_PAGE_W;
	end
	REFRESH_W: begin
	if(cmdack) begin             
		STATE<=IDLE_WR;
		end
	else
		STATE<=REFRESH_W;
	end
	
//PAGE READ BURST TEST    
	PAGE_READ:begin
		if(cmdack)    
			STATE<=BURST_READ;
		else 
			STATE<=PAGE_READ;
		Burst_cnt<=0;
		RCDCL_CNT<=0;
                end
                
	BURST_READ:begin
	if(Burst_cnt==('d6))
		s_enable <= 1; 
	else if(Burst_cnt==('d180-3))//BL+RCD+CL
		STATE<=BT;
	else
		STATE<=BURST_READ;
	Burst_cnt<=Burst_cnt+1;
	end
	
	BT:
	if(cmdack)
		STATE<=LAST_DATA;                       
	else
		STATE<=BT;                            
	LAST_DATA:
	STATE<=CLOSE_PAGE_R;

	CLOSE_PAGE_R:begin
	if(cmdack)
		STATE<=REFRESH_R;
	else
		STATE<=CLOSE_PAGE_R;
		
	if(RCDCL_CNT=='d2)
		s_enable<=0;
	else
		RCDCL_CNT<=RCDCL_CNT+1;	
	end
	
	REFRESH_R:begin
	if(cmdack)begin              
		STATE<=IDLE_WR;
		end
	else
		STATE<=REFRESH_R;
	end
	
	default:
	STATE<=IDLE;

	endcase
end

//generate the addr to the sdr_sdram_controller
always @ (STATE or w_page or r_page or r_ba or w_ba)
case(STATE)
	PRECHARGE:	addr = 'h1f0000;
	LOAD_MR:	addr = 'h37;
	LOAD_R2:	addr = 'h5F6;
	LOAD_R1:	addr = 'h12F; //'h10f
	PAGE_WRITE:	addr = {w_ba,w_page,8'b0};//PAGE_WRITE
	PAGE_READ:	addr = {r_ba,r_page,8'b0};
	BT_W:		addr = {w_ba,19'b0};    
	CLOSE_PAGE_W:	addr = {w_ba,19'b0};
	CLOSE_PAGE_R:	addr = {r_ba,19'b0};
	BT:		addr = {r_ba,19'b0};
	default:	addr = 'h0;
endcase

reg	s_ack;
always @ (posedge clk or negedge rst)
if(!rst)
	s_ack <= 0;
else
	s_ack <= STATE[13];

reg	r_ack;
always @ (posedge clk or negedge rst)
if(!rst)
	r_ack <= 0;
else
	r_ack <= STATE[9];
endmodule