sender_vga.v

视频采集

`timescale 1ns / 1ns

module sender_vga(	
	rst,						//main reset
	clk,				     	       //system clock
                
	hsin,
	vsin,
	blankin,
	blank_NTSC,

	pixel_R,
	pixel_G,
	pixel_B,
	        
	send_ram_rdb_raw,
	send_ram_rdb_mask,
	
	send_ram_rab_raw,
	send_ram_rab_mask,
               
	s_req_raw,
	s_ack_raw,
	
	s_req_mask,
	s_ack_mask,
        
	hsout,
	vsout,
	blankout,
	
	mask_read_ena,
	send_finish
              );						


/***input and output ***/
input	rst,clk,s_ack_mask,s_ack_raw;
input	hsin,vsin,blankin;
input	blank_NTSC;

input	[31:0]	send_ram_rdb_raw;
input	[7:0]	send_ram_rdb_mask;

output	[7:0]	pixel_R;
output	[7:0]	pixel_G;
output	[7:0]	pixel_B;
output	[8:0]	send_ram_rab_raw;
output	[8:0]	send_ram_rab_mask;

output	hsout;
output	vsout;
output	blankout;

output	s_req_raw;
output	s_req_mask;

input	mask_read_ena;
input	send_finish;
reg	s_req_raw;
reg	s_req_mask;

reg	[7:0]	pixel_R;
reg	[7:0]	pixel_G;
reg	[7:0]	pixel_B;

reg	hsout_reg;
reg	hsout;
reg	vsout_reg;
reg	vsout;
reg	blankout;
reg	blankout_reg;
reg	blank_ntsc_reg1;
reg	blank_ntsc_reg;
reg   [7:0]   mask_db_reg1,mask_db_reg;   
always @ (posedge clk) begin
	hsout_reg <= hsin;
	hsout <= hsout_reg;
	
	vsout_reg <= vsin;
	vsout <= vsout_reg;
	
	blankout_reg <= blankin;	
	blankout <= blankout_reg;
	
	blank_ntsc_reg1 <= blank_NTSC;
	blank_ntsc_reg <= blank_ntsc_reg1;
	
	mask_db_reg1 <= send_ram_rdb_mask;
	mask_db_reg <= mask_db_reg1;	
	end
reg	[3:0]	STATE,next;

always @ (posedge clk or negedge rst)
if(!rst)
	STATE <= 4'b1;
else
	STATE <= next;
	
always @ (STATE or blank_ntsc_reg1 or blank_ntsc_reg) begin//(STATE or blankout_reg or blankout) begin
next = 4'b0;
case(1'b1)
	STATE[0]: if(blank_ntsc_reg1)//(blankout_reg)
			next[1] = 1'b1;
		  else
		  	next[0] = 1'b1;
	STATE[1]: if(!blank_ntsc_reg)//(!blankout)
			next[0] = 1'b1;
		  else
		  	next[2] = 1'b1;
	STATE[2]: next[1] = 1'b1;
	STATE[3]:;
endcase
end
wire	[7:0]	R_color,G_color,B_color;
reg	[7:0]	y0,cb,cr,y1;
always @ (posedge clk) begin
	y0 <= send_ram_rdb_raw[15:8];//((send_ram_rdb_mask[7:6]=='d0)|mask_read_ena)?send_ram_rdb_raw[31:24]:send_ram_rdb_mask[7:6];//8'hfe;//send_ram_rdb_mask[3]?send_ram_rdb_raw[23:16]:'d255;
	cr <= send_ram_rdb_raw[23:16];//((send_ram_rdb_mask[5:4]=='d0)|mask_read_ena)?send_ram_rdb_raw[23:16]:send_ram_rdb_mask[5:4];//8'h80;//[31:24];
	cb <= send_ram_rdb_raw[7:0];//((send_ram_rdb_mask[1:0]=='d0)|mask_read_ena)?send_ram_rdb_raw[7:0]:send_ram_rdb_mask[1:0];//8'h80;//[15:8];
	y1 <= send_ram_rdb_raw[31:24];//((send_ram_rdb_mask[3:2]=='d0)|mask_read_ena)?send_ram_rdb_raw[15:8]:send_ram_rdb_mask[3:2];//8'hfe;//send_ram_rdb_mask[1]?send_ram_rdb_raw[7:0]:'d255;
end

rom_color_gen_RGB color_gen0(
	.in({mask_db_reg1[5:4],mask_db_reg1[1:0]}),
	.R_out(R_color),
	.G_out(G_color),
	.B_out(B_color)
	);
	
wire	[9:0]	y0_out,y1_out,cr_1p596,cb_2p017;
wire	[8:0]	cr_0p813,cb_0p392;
rom1p164_Y u0(
	.in(y0),
	.out(y0_out)
);	
rom1p596_Cr u1(
	.in(cr),
	.out(cr_1p596)
);	
rom0p813_Cr u2(
	.in(cr),
	.out(cr_0p813)
);
rom0p392_Cb u3(
	.in(cb),
	.out(cb_0p392)
);
rom2p017_Cb u4(
	.in(cb),
	.out(cb_2p017)
);
rom1p164_Y u5(
	.in(y1),
	.out(y1_out)
);

wire	[11:0]	sum1 =  y0_out + cr_1p596;
wire	[9:0]	r_reg0 = (sum1 > 9'd446)?(sum1-9'd446):'d0;

wire	[11:0]	sum2 = y0_out + 9'd271;
wire	[11:0]	sum3 = cr_0p813 + cb_0p392;
wire	[9:0]	g_reg0 = (sum2 > sum3)?(sum2 - sum3):0;

wire	[11:0]	sum4 = y0_out + cb_2p017;
wire	[9:0]	b_reg0 = (sum4 > 10'd554)?(sum4 - 10'd554):0;	

wire	[11:0]	sum5 =  y1_out + cr_1p596;
wire	[9:0]	r_reg1 = (sum5 > 9'd446)?(sum5-9'd446):'d0;

wire	[11:0]	sum6 = y1_out + 9'd271;
wire	[11:0]	sum7 = cr_0p813 + cb_0p392;
wire	[9:0]	g_reg1 = (sum6 > sum7)?(sum6 - sum7):0;

wire	[11:0]	sum8 = y1_out + cb_2p017;
wire	[9:0]	b_reg1 = (sum8 > 10'd554)?(sum8 - 10'd554):0;	

always @ (posedge clk or negedge rst)
if(!rst) begin
	pixel_R <= 0;
	pixel_G <= 0;
	pixel_B <= 0;
	end
else if(STATE[1]) begin
	pixel_R <= blank_ntsc_reg ? (mask_db_reg1[6] ? R_color:(r_reg1[9]?8'd255:r_reg1[8:1])):8'h0;
	pixel_G <= blank_ntsc_reg ? (mask_db_reg1[6] ? G_color:(g_reg1[9]?8'd255:g_reg1[8:1])):8'h0;
	pixel_B <= blank_ntsc_reg ? (mask_db_reg1[6] ? B_color:(b_reg1[9]?8'd255:b_reg1[8:1])):8'h0;
	end
else if(STATE[2]) begin
	pixel_R <= blank_ntsc_reg ? (mask_db_reg1[2] ?  R_color:(r_reg0[9]?8'd255:r_reg0[8:1])):8'h0;
	pixel_G <= blank_ntsc_reg ? (mask_db_reg1[2] ?  G_color:(g_reg0[9]?8'd255:g_reg0[8:1])):8'h0;
	pixel_B <= blank_ntsc_reg ? (mask_db_reg1[2] ?  B_color:(b_reg0[9]?8'd255:b_reg0[8:1])):8'h0;
	end
else begin
	pixel_R <= 0;
	pixel_G <= 0;
	pixel_B <= 0;
	end
	
reg	[7:0]	send_ram_rab_reg1,send_ram_rab_reg2;
reg	send_ram_rab_hbit1,send_ram_rab_hbit2;


always @ (posedge clk or negedge rst)
if(!rst)
	send_ram_rab_reg1 <= 0;
else if(blank_ntsc_reg1) begin//if(blankout_reg) begin
	
	if(STATE[1]) begin	
		if(send_ram_rab_reg1 == 'd179)
			send_ram_rab_reg1 <= 0;
		else
			send_ram_rab_reg1 <= send_ram_rab_reg1 + 1;
		end
	end
else
	send_ram_rab_reg1 <= 0;

always @ (posedge clk or negedge rst)
if(!rst)
	send_ram_rab_hbit1 <= 0;
else if(send_ram_rab_reg1 == 'd179 && STATE[1])
	send_ram_rab_hbit1 <= ~send_ram_rab_hbit1;
else if(vsout)
	send_ram_rab_hbit1 <= 0;

wire	[8:0]	send_ram_rab_mask = {send_ram_rab_hbit1,send_ram_rab_reg1};
//wire	[8:0]	send_ram_rab_raw = send_ram_rab_mask;


always @ (posedge clk or negedge rst)
if(!rst)
	send_ram_rab_reg2 <= 0;
else if(blank_ntsc_reg1) begin//if(blankout_reg) begin
	
	if(STATE[1]) begin	
		if(send_ram_rab_reg2 == 'd179 && !send_ram_rab_hbit1)
			send_ram_rab_reg2 <= 0;
		else
			send_ram_rab_reg2 <= send_ram_rab_reg2 + 1;
		end
	end
else
	send_ram_rab_reg2 <= 0;

always @ (posedge clk or negedge rst)
if(!rst)
	send_ram_rab_hbit2 <= 0;
else if(send_ram_rab_reg2 == 'd179 && STATE[1] && !send_ram_rab_hbit1)
	send_ram_rab_hbit2 <= ~send_ram_rab_hbit2;
else if(vsout)
	send_ram_rab_hbit2 <= 0;
else if(STATE[0])
	send_ram_rab_hbit2 <= send_ram_rab_hbit1;
		
wire	[8:0]	send_ram_rab_raw = {send_ram_rab_hbit2,send_ram_rab_reg2};

always @ (posedge clk or negedge rst)
if(!rst)
	s_req_raw <= 0;
else if((send_ram_rab_reg2=='d30 || (!vsout_reg & vsout)) && !send_finish)
	s_req_raw <= 1;
else if(s_ack_raw)
	s_req_raw <= 0;

always @ (posedge clk or negedge rst)
if(!rst)
	s_req_mask <= 0;
else if((send_ram_rab_reg2=='d30 || (!vsout_reg & vsout)) && !send_finish)
	s_req_mask <= 1;
else if(s_ack_mask)
	s_req_mask <= 0;
	
endmodule