image0109.v

视频采集

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/* Title          :	virtual image source                          */
/* Project        :	virtual source                                */
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// File name      :  image0109.v 
// Purpose        :  在芯片内部产生352×288的象素数据和时序信号  
// Author<email>  :  [e-mail]
// Created On     :  2003/01/09 
// Last update    :	 2003/01/09 
// Platform :     :	 Windows2000 
// Simulators     :	 MaxplussII 10.1 
// Synthesizers   :	 MaxplussII 10.1 
// Targets Device :	 (MAX7000AE)EPM7128AETC100-10 
// Comments       :  -
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module image0109(
	rst,						
	clk25m,
	qd,
	hsync,
	vsync,
	odd_even_out
);
/***input and output ***/
input	rst,clk25m;
output	[7:0]	qd;
output	hsync,vsync,odd_even_out;
/***reg***/
reg	[7:0]qd;
reg	hsync,vsync,odd_even_out;
reg	[10:0]	bit_cnt;
reg	[8:0]	h_cnt;
reg	hsync_reg;


always @ (posedge clk25m or negedge rst)
if(!rst)
	bit_cnt <= 0;
else if(bit_cnt == 'd1600)
	bit_cnt <= 0;
else
	bit_cnt <= bit_cnt + 1;

always @ (posedge clk25m or negedge rst)
if(!rst)
	hsync <= 0;
else if(bit_cnt < 'd1450 && bit_cnt >= 'd10)
	hsync <= 1;
else
	hsync <= 0;

always @ (posedge clk25m)
hsync_reg <= hsync;

always @ (posedge clk25m or negedge rst)
if(!rst)
	h_cnt <= 0;
else if(hsync_reg && !hsync) begin
	if(h_cnt == 'd311)
		h_cnt <= 0;
	else
		h_cnt <= h_cnt + 1;
	end

always @ (posedge clk25m or negedge rst)
if(!rst)
	vsync <= 0;
else if(h_cnt >= 'd10 && h_cnt < 'd298)
	vsync <= 1;
else
	vsync <= 0;

always @ (posedge clk25m or negedge rst)
if(!rst)
	odd_even_out <= 0;
else if(h_cnt == 'd310 && bit_cnt == 'd1000)
	odd_even_out <= ~odd_even_out;

always @ (posedge clk25m or negedge rst)
if(!rst)
	qd <= 0;
else if(hsync & vsync)
	qd <= qd + 1;
else if(!vsync)
	qd <= 0;
	
endmodule