datacnl_dsp.v.bak

视频采集

	
wire	[10:0]	r_page_vga = r_ba0_vga ? r_page_vga_even : r_page_vga_odd;
wire	[10:0]	r_page_mask = mode_vga ? r_page_vga : r_page_video;
wire	[10:0]	r_page = trans_raw_busy ? r_page_raw : r_page_mask;

reg	raw_send_int;
always @ (posedge clk or negedge rst)
if(!rst)
	raw_send_int <= 1;
else if(trans_raw_busy && r_page_raw=='d1 && !r_ba_raw)
	raw_send_int <= 0;
else if(r_page_raw=='d3)
	raw_send_int <= 1;
//********************************************************************************//
//***********************the state machine****************************************//				
//********************************************************************************//
always @(posedge clk or negedge rst)
begin
if(!rst) begin
        STATE<=IDLE;
		s_enable<=0;
//	send_cnl<=0;
        RCDCL_CNT<=0;
        Burst_cnt<=0;
        trans_raw_busy <= 0;
		mask_send_ack <= 0;
	end
else
     case(STATE)
	IDLE:
	if(start_read)
		STATE<=PRECHARGE;
	else
		STATE<=IDLE;
		
	PRECHARGE:
	if(cmdack)
		STATE<=PRECHARGE_ACK;
	else
		STATE<=PRECHARGE;
		
	PRECHARGE_ACK:
		STATE<=LOAD_MR;
		
	LOAD_MR:
	if(cmdack)  
		STATE<=LOAD_MR_ACK;
	else
		STATE<=LOAD_MR;
		
	LOAD_MR_ACK:
		STATE<=LOAD_R2;
		
	LOAD_R2:
	if(cmdack)
 		STATE<=LOAD_R2_ACK;
	else
		STATE<=LOAD_R2;
		
	LOAD_R2_ACK:
		STATE<=LOAD_R1;
	LOAD_R1:
	if(cmdack)
		STATE<=IDLE_WR;
	else
		STATE<=LOAD_R1;

//page write burst
	IDLE_WR:                //9
	if(!vsync_vga_reg & vsync_vga_reg1) begin
		if(raw_mode & !trans_raw_busy) begin
			STATE<=IDLE_W;
			trans_raw_busy <= 1;
			end
		else if(trans_raw_busy) begin
			STATE<=IDLE_R;
			end  	
		else if(mask_mode) begin
			STATE<=IDLE_W;
			mask_send_ack <= 1;
			end		
		else begin
			STATE<=IDLE_R;
			end
		end  
	else begin
		STATE<=IDLE_WR;
		end
	IDLE_W: begin						//9
	if((r_req_raw & trans_raw_busy) | (r_req_mask & !trans_raw_busy))				//两个申请信号不会同时到
		STATE <= PAGE_WRITE;
	else if(vsync_reg & !vsync_reg1 & !w_ba[0] & !mask_send_ack) begin //  	//收完两场之后返回
		if(trans_raw_busy)
			STATE <= PAGE_READ;
		else
			STATE <= IDLE_WR;
//		mask_send_ack <= 0;
		end
	else
		STATE <= IDLE_W;
	end
	PAGE_WRITE: //10
	if(cmdack) begin
		STATE<=BURST_WRITE; 
		Burst_cnt<=0;
		end
	else
		STATE<=PAGE_WRITE;  
		
	BURST_WRITE: begin
	if(Burst_cnt==(8'd177))//256-BL
		STATE<=BT_W;
	else
		STATE<=BURST_WRITE;
	Burst_cnt<=Burst_cnt+1;
	end  
	
	BT_W:begin          //12
	if(cmdack)
		STATE<=WAIT_ACK_W_T;
	else
		STATE<=BT_W;
	end

	WAIT_ACK_W_T:begin
	STATE<=CLOSE_PAGE_W;
	end        
	 
//CLOSE CURRENT PAGE                       
	CLOSE_PAGE_W:begin
	if(cmdack)
		STATE<=REFRESH_W;
	else
		STATE<=CLOSE_PAGE_W;
	end
	REFRESH_W: begin
	if(cmdack) begin 		
		if(w_ba[0]  &&  w_page_mask == 'd0 && mask_send_ack) begin
			STATE<=IDLE_WR;
			mask_send_ack <= 0;
			end
		else            
			STATE<=IDLE_W;
		end
	else
		STATE<=REFRESH_W;
	end
	
//PAGE READ BURST TEST
	IDLE_R: begin                //9
	if((s_req_raw & trans_raw_busy) | (s_req_mask & !trans_raw_busy))
		STATE<=PAGE_READ;
	else if(vsync_reg & !vsync_reg1 & !trans_raw_busy) begin//& !r_ba[0] 
		STATE<=IDLE_WR;
		end
	else
		STATE<=IDLE_R;		
	end  
	PAGE_READ:begin
		if(cmdack)    
			STATE<=BURST_READ;
		else 
			STATE<=PAGE_READ;
		Burst_cnt<=0;
		RCDCL_CNT<=0;
                end
                
	BURST_READ:begin
	if(Burst_cnt==('d6))
		s_enable <= 1; 
	else if(Burst_cnt==('d180-3))//BL+RCD+CL
		STATE<=BT;
	else
		STATE<=BURST_READ;
	Burst_cnt<=Burst_cnt+1;
	end
	
	BT:
	if(cmdack)
		STATE<=LAST_DATA;                       
	else
		STATE<=BT;                            
	LAST_DATA:
	STATE<=CLOSE_PAGE_R;

	CLOSE_PAGE_R:begin
	if(cmdack)
		STATE<=REFRESH_R;
	else
		STATE<=CLOSE_PAGE_R;
		
	if(RCDCL_CNT=='d2)
		s_enable<=0;
	else
		RCDCL_CNT<=RCDCL_CNT+1;	
	end
	
	REFRESH_R:begin
	if(cmdack)begin              			
		if(r_ba[0]  &&  r_page_raw == 'd0 && trans_raw_busy) begin
			STATE<=IDLE_WR;
			trans_raw_busy <= 0;
			end
		else
			STATE<=IDLE_R;
		end			
	else
		STATE<=REFRESH_R;
	end
	
	default:
	STATE<=IDLE;

	endcase
end

//generate the addr to the sdr_sdram_controller
reg	[20:0]	addr;
always @ (STATE or w_page or r_page or r_ba or w_ba)
case(STATE)
	PRECHARGE:	addr = 'h1f0000;
	LOAD_MR:	addr = 'h37;
	LOAD_R2:	addr = 'h5F6;
	LOAD_R1:	addr = 'h12F; //'h10f
	PAGE_WRITE:	addr = {w_ba,w_page,8'b0};//PAGE_WRITE
	PAGE_READ:	addr = {r_ba,r_page,8'b0};
	BT_W:		addr = {w_ba,19'b0};    
	CLOSE_PAGE_W:	addr = {w_ba,19'b0};
	CLOSE_PAGE_R:	addr = {r_ba,19'b0};
	BT:		addr = {r_ba,19'b0};
	default:	addr = 'h0;
endcase


reg	s_ack;
always @ (posedge clk or negedge rst)
if(!rst)
	s_ack <= 0;
else
	s_ack <= STATE[13];
wire	s_ack_raw  = s_ack & trans_raw_busy;	
wire	s_ack_mask = s_ack & !trans_raw_busy;


reg	r_ack;
always @ (posedge clk or negedge rst)
if(!rst)
	r_ack <= 0;
else
	r_ack <= STATE[9];
wire	r_ack_raw = r_ack & trans_raw_busy;
wire	r_ack_mask = r_ack &  !trans_raw_busy;
//*************************************************************************************//
//*************************  r_ram_rab  ***********************************************//
//*************************************************************************************//
reg	[7:0]	r_ram_rab_reg;
always @ (posedge clk or negedge rst)
if(!rst)
	r_ram_rab_reg <= 0;
else if((STATE[9]&cmdack)|STATE[10])
	r_ram_rab_reg <= r_ram_rab_reg + 1;
else if(STATE12_reg)
	r_ram_rab_reg <= 0;

reg	r_ram_rab_hbit;
always @ (posedge clk or negedge rst)
if(!rst)
	r_ram_rab_hbit <= 0;
else if(r_ram_rab_reg == 'd179 && STATE12_reg)
	r_ram_rab_hbit <= ~r_ram_rab_hbit;
else if(trans_raw_busy)
	r_ram_rab_hbit <= 0;

wire	[8:0]	r_ram_rab_mask = {r_ram_rab_hbit,r_ram_rab_reg};
wire	[7:0]	r_ram_rab_raw = r_ram_rab_reg;
//***************************************************************************************//
//****************************  s_ram_wab   *********************************************//
//***************************************************************************************//
reg	[7:0]	s_ram_wab_reg;
reg	s_ram_wab_hbit;
wire	[8:0]	s_ram_wab_mask = {s_ram_wab_hbit,s_ram_wab_reg};
wire	[7:0]	s_ram_wab_raw = s_ram_wab_reg;
always @ (posedge clk or negedge rst)
if(!rst) begin
	s_ram_wab_reg<='d0;
	end
else  begin
	if(s_enable)
		s_ram_wab_reg<=s_ram_wab_reg+1;
	else
		s_ram_wab_reg<=0;
	end

	
always @ (posedge clk or negedge rst)
if(!rst) begin
	s_ram_wab_hbit<=0;
	end
else  begin
	if(STATE19_reg & cmdack)
		s_ram_wab_hbit <= ~s_ram_wab_hbit;
	if(mode_vga) begin
		if(!vsync_vga_reg)
			s_ram_wab_hbit <= 0;
		end
	else begin
		if(!vsync_reg)
			s_ram_wab_hbit <= 0;
		end
	end	
//***************************************************************************************//
//***************************************************************************************//
reg	[8*10:0]	cmd_name;
always @ cmd
case (cmd)
  'b000: cmd_name="NOP";
  'b001: cmd_name="READA";
  'b010: cmd_name="WRITEA";
  'b011: cmd_name="REFRESH";
  'b100: cmd_name="PRECHARGE";
  'b101: cmd_name="LOAD_MODE";
  'b110: cmd_name="LOAD_REG1";
  'b111: cmd_name="LOAD_REG2";
  endcase
  
reg	[8*12:0]	state_name;  
always @ STATE
case(STATE)
 	PRECHARGE:	state_name="PRECHARGE";
	PRECHARGE_ACK:	state_name="PRECHARGE_ACK";
	LOAD_MR:	state_name="LOAD_MR";
	LOAD_MR_ACK:	state_name="LOAD_MR_ACK";
	LOAD_R2:	state_name="LOAD_R2";
	LOAD_R2_ACK:	state_name="LOAD_R2_ACK";
	LOAD_R1:	state_name="LOAD_R1";
	IDLE_WR:	state_name="IDLE_WR";
 	PAGE_WRITE:	state_name="PAGE_WRITE";
	BURST_WRITE:	state_name="BURST_WRITE";
	BT_W:		state_name="BT_W";
	CLOSE_PAGE_W:	state_name="CLOSE_PAGE_W";
	CLOSE_PAGE_R:	state_name="CLOSE_PAGE_R";
	PAGE_READ:	state_name="PAGE_READ";
	BURST_READ:	state_name="BURST_READ";
	BT:		state_name="BT";
	LAST_DATA:	state_name="LAST_DATA";
	REFRESH_R:	state_name="REFRESH_R";
	REFRESH_W:	state_name="REFRESH_W";
	IDLE_R:		state_name="IDLE_R";
	IDLE_W:		state_name="IDLE_W"; 
	default:	state_name="default";
	endcase
//***************************************************************************************//
//***************************************************************************************//
//***************************************************************************************//
endmodule