datacnl_dsp.v.bak

视频采集

module datacnl_dsp(	
	clk,
	rst,

	r_ram_rdb_raw,	
	r_ram_rab_raw,	
	r_req_in_raw,
	r_ack_raw,
	
	r_ram_rdb_mask,	
	r_ram_rab_mask,	
	r_req_in_mask,
	r_ack_mask,
	
	s_ram_wdb_mask,
	s_ram_wab_mask,
	s_ram_wen_mask,	
	s_req_in_mask,
	s_ack_mask,
	
	s_ram_wdb_raw,
	s_ram_wab_raw,
	s_ram_wen_raw,	
	s_req_in_raw,
	s_ack_raw,
	
	cmd,
	cmdack,
	addr,
	datain,
	dataout,

	start_read,
	mode_vga_in,
				
	vsync,
	vsync_vga,
	
	raw_demand,
	raw_send_int,
	
	mask_demand,
	mask_send_ack,
	mask_mode,
	mask_read_ena
                );

input	clk;
input	rst;

input	[15:0]	r_ram_rdb_raw;	
output	[7:0]	r_ram_rab_raw;	
input	r_req_in_raw;
output	r_ack_raw;
	
input	[7:0]	r_ram_rdb_mask;	
output	[8:0]	r_ram_rab_mask;	
input	r_req_in_mask;
output	r_ack_mask;
	
output	[7:0]	s_ram_wdb_mask;
output	[8:0]	s_ram_wab_mask;
output	s_ram_wen_mask;	
input	s_req_in_mask;
output	s_ack_mask;
	
output	[15:0]	s_ram_wdb_raw;
output	[7:0]	s_ram_wab_raw;
output	s_ram_wen_raw;	
input	s_req_in_raw;
output	s_ack_raw;
	
output	[2:0]	cmd;
input	cmdack;
output	[20:0]	addr;
output	[15:0]	datain;
input	[15:0]	dataout;

input	start_read;
input	mode_vga_in;
				
input	vsync;
input	vsync_vga;
	
input	raw_demand;
output	raw_send_int;
	
input	mask_demand;
output	mask_send_ack;
output	mask_mode;
output	mask_read_ena;
//---------port variables declaration-----------//
// State parameters used in MAIN  STATE MACHINE
parameter 
	IDLE		=23'b000_0000_0000_0000_0000_0001,
	PRECHARGE	=23'b000_0000_0000_0000_0000_0010,
	PRECHARGE_ACK	=23'b000_0000_0000_0000_0000_0100,    
	LOAD_MR		=23'b000_0000_0000_0000_0000_1000,
	LOAD_MR_ACK	=23'b000_0000_0000_0000_0001_0000,
	LOAD_R2		=23'b000_0000_0000_0000_0010_0000,
	LOAD_R2_ACK	=23'b000_0000_0000_0000_0100_0000,
	LOAD_R1		=23'b000_0000_0000_0000_1000_0000,
                          
	IDLE_WR		=23'b000_0000_0000_0001_0000_0000,    
	PAGE_WRITE	=23'b000_0000_0000_0010_0000_0000,
	BURST_WRITE	=23'b000_0000_0000_0100_0000_0000,
	BT_W		=23'b000_0000_0000_1000_0000_0000,
	WAIT_ACK_W_T	=23'b000_0000_0001_0000_0000_0000,
                         
	PAGE_READ	=23'b000_0000_0010_0000_0000_0000,
	BURST_READ	=23'b000_0000_0100_0000_0000_0000,
	BT		=23'b000_0000_1000_0000_0000_0000,
	LAST_DATA	=23'b000_0001_0000_0000_0000_0000,
	CLOSE_PAGE_W	=23'b000_0010_0000_0000_0000_0000,
	REFRESH_W       =23'b000_0100_0000_0000_0000_0000,
	CLOSE_PAGE_R    =23'b000_1000_0000_0000_0000_0000,
	REFRESH_R       =23'b001_0000_0000_0000_0000_0000,
	IDLE_W		=23'b010_0000_0000_0001_0000_0000,
	IDLE_R		=23'b100_0000_0000_0001_0000_0000;
	
parameter RCD='D3,CL='D3,BL='d180;//H_PIXELS>>2;

reg	s_enable;
reg	[22:0]	STATE;

reg	[7:0]	Burst_cnt;
reg	[1:0]	RCDCL_CNT;


//reg	send_cnl;

reg	mode_vga;
reg	vsync_reg,vsync_vga_reg,vsync_reg1,vsync_vga_reg1;
reg	s_req_mask,r_req_raw,r_req_mask,s_req_raw;
reg	s_req_mask1,r_req_raw1,r_req_mask1,s_req_raw1;
always @ (posedge clk)
begin
	mode_vga <= mode_vga_in;
	vsync_reg <= vsync_reg1;
	vsync_reg1 <= vsync;
	vsync_vga_reg1 <= vsync_vga;
	vsync_vga_reg <= vsync_vga_reg1;
	
	s_req_mask1 <= s_req_in_mask;
	r_req_raw1 <= r_req_in_raw;
	r_req_mask1 <= r_req_in_mask;
	s_req_raw1 <= s_req_in_raw;
	
	s_req_mask <= s_req_mask1;
	r_req_raw <= r_req_raw1;
	r_req_mask <= r_req_mask1;
	s_req_raw <= s_req_raw1;
end
	
reg	raw_mode;
reg	trans_raw_busy; 

//**********************************************************************************//
always @ (posedge clk or negedge rst)
if(!rst)
	raw_mode <= 0;
else if(raw_demand)
	raw_mode <= 1;
else if(trans_raw_busy)
	raw_mode <= 0;
//**********************************************************************************//
//**********************************************************************************//
reg	mask_mode;
reg	mask_send_ack;
always @ (posedge clk or negedge rst)
if(!rst)
	mask_mode <= 0;
else if(mask_demand)
	mask_mode <= 1;
else if(mask_send_ack)
	mask_mode <= 0;
	
reg	mask_read_ena = !(trans_raw_busy|mask_send_ack);
//**********************************************************************************//
//**********************************************************************************//
//********************transfer the data bus*****************************************//
reg	[15:0]	s_ram_wdb_raw;
reg	[7:0]	s_ram_wdb_mask;
always @ (posedge clk) begin	
	s_ram_wdb_raw <= dataout;
	s_ram_wdb_mask <= dataout[7:0];//s_ram_wdb_mask <= s_ram_wen_mask ? (s_ram_wdb_mask +1) : 'd0;//
	end
assign	datain = trans_raw_busy ? r_ram_rdb_raw : {8'd0,r_ram_rdb_mask};
//**********************************************************************************//
//**********************************************************************************//

reg	STATE12_reg,STATE16_reg,STATE8_reg,STATE19_reg;
always @ (posedge clk) begin
	STATE12_reg <= STATE[12];
	STATE16_reg <= STATE[16];
	STATE8_reg  <= STATE[8];
	STATE19_reg <= STATE[19];
end
	
//generate the send wen signal 
assign s_ram_wen_raw = s_enable & trans_raw_busy;
assign s_ram_wen_mask = s_enable & !trans_raw_busy;



parameter	NOP       ='b000,
		READA     ='b001,
		WRITEA    ='b010,
		ARF       ='b011,
		PRECHRG   ='b100,
		LOAD_MODE ='b101,
		LOAD_REG1 ='b110,
		LOAD_REG2 ='b111;
		
//generate the cmd to the sdr_sdram_controller
reg	[2:0]	cmd;
always @ (STATE)
case(STATE)    
	PRECHARGE:	cmd = PRECHRG;
	LOAD_MR:	cmd = LOAD_MODE;
	LOAD_R2:	cmd = LOAD_REG2;
	LOAD_R1:	cmd = LOAD_REG1;
	PAGE_WRITE:	cmd = WRITEA;
	BT_W:		cmd = PRECHRG;
	CLOSE_PAGE_W:	cmd = PRECHRG;
	CLOSE_PAGE_R:	cmd = PRECHRG;
	PAGE_READ:	cmd = READA;
	BT:		cmd = PRECHRG;
	REFRESH_W:	cmd = ARF;
	REFRESH_R:	cmd = ARF;
	default:	cmd = NOP;
endcase

//*****************************************************************************//
//**************************w_ba & w_page**************************************//
//*****************************************************************************//
reg	[10:0]	w_page_raw,w_page_mask;
always @ (posedge clk or negedge rst)
if(!rst) begin
	w_page_raw <= 0;
	w_page_mask <= 0;
	end
else if(STATE12_reg) begin
	if(trans_raw_busy)
		w_page_raw <= w_page_raw + 1;
	else
		w_page_mask <= w_page_mask + 1;
	end
else begin
	if(w_page_raw == 'd960)
		w_page_raw <= 0;
	else if(w_page_mask == 'd480)
		w_page_mask <= 0;
	end

wire	[10:0]	w_page = trans_raw_busy ? w_page_raw : w_page_mask;

reg	w_ba_mask,w_ba_raw;
always @ (posedge clk or negedge rst)
if(!rst) begin
	w_ba_mask <= 0;
	w_ba_raw <= 0;
	end
else if(STATE[18] & cmdack) begin
	if(w_page_raw == 0 && trans_raw_busy)//'d959
		w_ba_raw <= ~w_ba_raw;
	else if(w_page_mask == 0 && mask_send_ack)//d479
		w_ba_mask <= ~w_ba_mask;
	end
	
wire	[1:0]	w_ba = trans_raw_busy ? {1'b0,w_ba_raw} : {1'b1,w_ba_mask};

//****************************************************************************//
//***********************  r_ba & r_page *************************************//
//****************************************************************************//
reg	[10:0]	r_page_raw;
always @ (posedge clk or negedge rst)
if(!rst) 
	r_page_raw <= 0;
else if(trans_raw_busy) begin
	if(STATE16_reg)
		r_page_raw <= r_page_raw + 1;
	else if(r_page_raw == 'd960)
		r_page_raw <= 0;
	end
	
reg	r_ba_raw;
always @ (posedge clk or negedge rst)
if(!rst) 
	r_ba_raw <= 0;
else if(trans_raw_busy && STATE[20] && cmdack) begin
	if( r_page_raw == 'd0)
		r_ba_raw <= ~r_ba_raw;
	end
	
reg	[10:0]	r_page_video;
reg	r_ba_video;
	
always @ (posedge clk or negedge rst)
if(!rst) 
	r_page_video <= 0;
else if(!mode_vga & !trans_raw_busy) begin
	if(STATE16_reg)
		r_page_video <= r_page_video + 1;
	else if(STATE8_reg & (!vsync_reg))
		r_page_video <= 0;
	end


always @ (posedge clk or negedge rst)
if(!rst)
	r_ba_video <= 0;
else if(!mode_vga & !trans_raw_busy) begin
	if(STATE8_reg & (!vsync_reg)) begin
		if(r_page_video != 0)
			r_ba_video<=~r_ba_video;
		end
	end				          				 


reg	r_ba0_vga,ba0_cnl;
always @ (posedge clk or negedge rst)
if(!rst) begin
	r_ba0_vga <= 0;
	ba0_cnl <= 0;
	end
else if(mode_vga & !trans_raw_busy) begin
	if(STATE[20] & cmdack) begin
		ba0_cnl <= ~ba0_cnl;
		if(ba0_cnl)
			r_ba0_vga <= ~r_ba0_vga;
		end	
	else if(!vsync_vga_reg) begin
		r_ba0_vga <= 0;
		ba0_cnl <= 0;
		end
	end

wire	[1:0]	r_ba_mask = mode_vga ? {1'b1,r_ba0_vga} : {1'b1,r_ba_video};
wire	[1:0]	r_ba = trans_raw_busy ? {1'b0,r_ba_raw} : r_ba_mask;
reg	[10:0]	r_page_vga_odd,r_page_vga_even;

always @ (posedge clk or negedge rst)
if(!rst) begin
	r_page_vga_odd <= 0;
	r_page_vga_even <= 0;
	end
else if(STATE16_reg & mode_vga & !trans_raw_busy) begin
	if(!r_ba0_vga)
		r_page_vga_odd <= r_page_vga_odd + 1;
	else
		r_page_vga_even <= r_page_vga_even + 1;
	end
else if(STATE8_reg & (!vsync_vga_reg)) begin
	r_page_vga_odd <= 0;
	r_page_vga_even <= 0;
	end