vga_out.v.bak

视频采集

/*******************************************************************/
/* Title          :	virtual image source                          */
/* Project        :	virtual source                                */
/*******************************************************************/

/*******************************************************************/
// File name      :  image0109.v 
// Purpose        :  在芯片内部产生352×288的象素数据和时序信号  
// Author<email>  :  [e-mail]
// Created On     :  2003/01/09 
// Last update    :	 2003/01/09 
// Platform :     :	 Windows2000 
// Simulators     :	 MaxplussII 10.1 
// Synthesizers   :	 MaxplussII 10.1 
// Targets Device :	 (MAX7000AE)EPM7128AETC100-10 
// Comments       :  -
/*******************************************************************/

/*******************************************************************/
/*测控研究所图像处理组   		   									   */
/*******************************************************************/

/*******************************************************************/
/* Revision History :											   */
/*******************************************************************/
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module vga_out(
	rst,						
	clk40m,
	vsin,
	
	blank,
	hsync,
	vsync,
	odd_even_out
);
/***input and output ***/
input	rst,clk40m;
input	vsin;

output	blank;
output	hsync,vsync,odd_even_out;
/***reg***/
reg	blank;
reg	hsync,vsync,odd_even_out;
reg	[10:0]	bit_cnt;
reg	[9:0]	h_cnt;
reg	hsync_reg;
reg	vsin_reg;

reg	vsin_reg1,vsin_reg2;

always @ (posedge clk40m) begin
vsin_reg <= vsin;
vsin_reg1 <= vsin_reg;
vsin_reg2 <= vsin_reg1;
end

reg	start;
always @ (posedge clk40m or negedge rst)
if(!rst)
	start <= 0;
else if(vsin_reg2 & !vsin_reg1)
	start <= 1;
	
reg	odd_even;
always @ (posedge clk40m or negedge start)
if(!start)
	odd_even <= 0;
else if(vsin_reg2 & !vsin_reg1)
	odd_even <= ~odd_even;
	
reg	sync_rst;

always @ (posedge clk40m or negedge start)
if(!start)
	sync_rst <= 0;
else if(vsin_reg2 & !vsin_reg1 & odd_even)
	sync_rst <= 0;
else 
	sync_rst <= 1;

		
always @ (posedge clk40m or negedge sync_rst)
if(!sync_rst)
	bit_cnt <= 0;
else if(bit_cnt == 'd1060)
	bit_cnt <= 0;
else
	bit_cnt <= bit_cnt + 1;

always @ (posedge clk40m or negedge sync_rst)
if(!sync_rst)
	hsync <= 0;
else if(bit_cnt < 'd170 && bit_cnt >= 'd40)
	hsync <= 1;
else
	hsync <= 0;

always @ (posedge clk40m) begin
hsync_reg <= hsync;
end

always @ (posedge clk40m or negedge sync_rst)
if(!sync_rst)
	h_cnt <= 0;
else if(bit_cnt=='d1060) begin
	if(h_cnt == 'd628)//'d20)
		h_cnt <= 0;
	else
		h_cnt <= h_cnt + 1;
	end

always @ (posedge clk40m or negedge sync_rst)
if(!sync_rst)
	vsync <= 0;
else if(h_cnt < 'd5 & h_cnt >'d0)
	vsync <= 1;
else
	vsync <= 0;

always @ (posedge clk40m or negedge rst)
if(!rst)
	odd_even_out <= 0;
else if(h_cnt == 'd2 && bit_cnt == 'd2)
	odd_even_out <= ~odd_even_out;



always @ (posedge clk40m or negedge sync_rst)
if(!sync_rst)
	blank <= 0;
else if((bit_cnt >='d260)&&(bit_cnt <'d1060)&&(h_cnt>'d27)&&(h_cnt<='d627))//&&(bit_cnt <'d892)
	blank <= 1;
else
	blank <= 0;

reg	blank_NTSC;
always @ (posedge clk40m or negedge sync_rst)
if(!sync_rst)
	blank_NTSC <= 0;
else if((bit_cnt >='d260)&&(bit_cnt <'d980)&&(h_cnt>'d27)&&(h_cnt<='d507))//&&(bit_cnt <'d892)
	blank_NTSC <= 1;
else
	blank_NTSC <= 0;	
endmodule