icrt0.s

T-monitor监控程序

;/*""FILE COMMENT""*************************************************************
;*       System Name : RENESAS T-Engine/micro T-Engine
;*       File Name   : icrt0.S
;*       Version     : 1.00.00
;*       Contents    : T-Monitor system startup
;*       Model       : SH7145 micro T-Engine
;*       CPU         : SH7145F
;*       Compiler    : Renesas SH-C
;*       OS          : T-Kernel
;*       note        : The Software is being delivered to you "AS IS" 
;*                   : and Renesas,whether explicitly or implicitly makes  
;*                   : no warranty as to its Use or performance. 
;*                   : RENESAS AND ITS SUPPLIER DO NOT AND CANNOT WARRANT 
;*                   : THE PERFORMANCE OR RESULTS YOU MAY OBTAIN  BY USING 
;*                   : THE SOFTWARE. AS TO ANY MATTER INCLUDING WITHOUT 
;*                   : LIMITATION NONINFRINGEMENT OF THIRD PARTY RIGHTS,
;*                   : MERCHANTABILITY, INTEGRATION, SATISFACTORY QUALITY, 
;*                   : OR FITNESS FOR ANY PARTICULAR PURPOSE.
;*
;*       Copyright (c) 2004 RENESAS TECHNOLOGY CORP. All Rights Reserved.
;*       AND RENESAS SOLUTIONS CORP. All Rights Reserved.
;*       history     : 2006.03.27 ver.1.00.00
;*""FILE COMMENT END""*********************************************************/

;/* BSC setting values */
BCR1_OFFSET:	.equ	0 ;/* 0xFFFF8620 (BSC_BASE) */
BCR2_OFFSET:	.equ	2 ;/* 0xFFFF8622 - BSC_BASE */
WCR1_OFFSET:	.equ	4 ;/* 0xFFFF8624-BSC_BASE */ 
WCR2_OFFSET:	.equ	6 ;/* 0xFFFF8626-BSC_BASE */

INTC_BASEADDR:	.equ	H'FFFF8358
ICR1_OFFSET:	.equ	0
ICR2_OFFSET:	.equ	H'FFFF8366 - INTC_BASEADDR

	.import _io_init
	.import _init_scinfo
	.import _DTBL
	.import _BTBL

	.section P,code
	.align	2
	.global	start
start:
;	/* SR Initial setting (SR.I=15) */
	mov.l	INIT_SR, r0
	ldc	r0, sr

;	/* Use the stack set by the boot loader */
	mov.l   S_int_stack_top,r15

;	/* Initialize module stanby registers */
;	/* MSTCR1 bit1(SCI1) available */
	mov.l   MSTCR1_ADDR,r1
	mov.w   MSTCR1_DATA,r0
	not     r0,r0
	mov.w   @r1,r2
	and     r2,r0
	mov.w   r0,@r1

;	/* MSTCR2 MTU,CMT available */
	add     #2,r1           ;/* R1:MSTCR2_ADDR */
	mov.w   MSTCR2_DATA,r0
	not     r0,r0
	mov.w   @r1,r2
	and     r2,r0
	mov.w   r0,@r1
	
;	/* Initialize BSC */
	mov.l	BSC_BASE,r0	;/* set BCR base addrress to GBR */
	ldc     r0,gbr

	mov.w	BCR1_DATA,r0   ;/* Initialize BCR1 */
	mov.w	r0,@(BCR1_OFFSET,gbr)

	mov.w	BCR2_DATA,r0   ;/* Initialize BCR2 */
	mov.w	r0,@(BCR2_OFFSET,gbr)

	mov.w	WCR1_DATA,r0   ;/* Initialize WCR1 */
	mov.w	r0,@(WCR1_OFFSET,gbr)

	mov.w	WCR2_DATA,r0   ;/* Initialize WCR2 */
	mov.w	r0,@(WCR2_OFFSET,gbr)

;	/* INTC */
	mov.l	INTC_BASE,r0	;/* set BCR base addrress to GBR */
	ldc     r0,gbr 

	mov  	#0,r0           
	mov.w	r0,@(ICR1_OFFSET,gbr) ;/* Initialize ICR1 */
	mov.w	r0,@(ICR2_OFFSET,gbr) ;/* Initialize ICR2 */

;	/* IO INIT */
	mov.l	IO_INIT, r0		;// Initialization at Port
	jsr	@r0
	nop

	mov.l	DATA_ORG, r1		;// Initialization of 'data' area (ROM startup)
	mov.l	@r1, r1
	mov.l	DATA_START, r2
	mov.l	@r2, r2
	mov.l	EDATA, r3
	mov.l	@r3, r3
	cmp/eq	r2, r3			;// If r2 != r3, start ROM
	bt/s	nocopy_data
	movt	r8			;// If start ROM, r8 = 0
  copy_data:
	cmp/hi	r2, r3
	bf	nocopy_data
	mov.l	@r1+, r0
	mov.l	r0, @r2
	bra	copy_data
	add     #4,r2        ;// delayed slot
  nocopy_data:
	
;	/* Clear 'bss' Area */
	mov	#0, r0		
	mov.l	BSS_TOP, r1
	mov.l	@r1, r1
	mov.l	BSS_END, r2
	mov.l	@r2, r2
	cmp/hi	r1, r2
	bf	nobss
	add	#4, r1
clrbss:
	cmp/hi	r1, r2
	bt/s	clrbss
	mov.l	r0, @-r2
nobss:

;	/* Clear 'SCAREA' */
	mov	#0, r0		
	mov.l	SCAREA_TOP, r1
	mov.l	SCAREA_END, r2
	cmp/hi	r1, r2
	bf	noscarea
	add	#4, r1
clrscarea:
	cmp/hi	r1, r2
	bt/s	clrscarea
	mov.l	r0, @-r2
noscarea:

;	/* SCINFO INIT */
	mov.l	INIT_SCINFO, r0		;// Initialization at Port
	jsr	@r0
	nop

;	/* regist T-Monitor function to Vector Table */
	mov.l	TMON_ENTRY, r0
	mov.l   TMON_VEC,   r1
	mov.l   r0,@r1

;	/* call Resetinit function */
	mov.l	RSTINIT, r0
	mov.l	@r0, r0
	cmp/eq  #0,r0
	bt      skip_rstinit
	nop
	jsr	@r0
	nop

skip_rstinit:

;	/* call T-Kernel startup */
	mov.l	KERNEL, r0
	mov.l	@r0, r0
	jsr	@r0
	nop

  l_end:				;// Not suppose to return from 'main,'
	bra	l_end			;// but, just in case, prepare for out of control.
	nop

		.align	4
;/* MST Address definition */
MSTCR1_ADDR:	.data.l	H'FFFF861C
MSTCR2_ADDR:	.data.l	H'FFFF861E
MSTCR1_DATA:	.data.w	H'0002 ;/* SCI1 available */
MSTCR2_DATA:	.data.w	H'3000 ;/* MTU,CMT available */

;/* BSC Address definition */
BSC_BASE:	.data.l	H'FFFF8620
BCR1_DATA:	.data.w	H'600F 
;/* BCR2_DATA:	.data.w	H'D5F7 */
BCR2_DATA:	.data.w	H'AAF7
WCR1_DATA:	.data.w	H'2533
WCR2_DATA:	.data.w	H'000F

INTC_BASE:	.data.l	H'FFFF8358

INIT_SR:	.data.l	H'F0
DATA_ORG:	.data.l	_DTBL
DATA_START:	.data.l	_DTBL + 8
EDATA:		.data.l	_DTBL + 12
BSS_TOP:	.data.l	_BTBL
BSS_END:	.data.l	_BTBL + 4
IO_INIT:	.data.l	_io_init
INIT_SCINFO:	.data.l	_init_scinfo
SCAREA_TOP:	.data.l	__SCAREA_start
SCAREA_END:	.data.l	__SCAREA_end

S_int_stack_top:	.data.l	H'FFFFFFFC ;// 19.Apr.2004

;/* Kernel Start address */
ROMINFO:	.equ	H'00000C00     ;/* Outer Flash top address */
KERNEL:		.data.l	ROMINFO+4      ;/* ROMInfo kernel start */
RSTINIT:	.data.l	ROMINFO+12     ;/* ROMInfo resetinit */

;/* T-Monitor vector address */
	.import	_tm_entry
TMON_ENTRY:	.data.l	_tm_entry
SCAREA:		.equ	H'FFFFE000     ;/* Inner RAM top address */
TMON_VEC:	.data.l	(SCAREA + 32)

	.section _SCAREA
	.align 4
__SCAREA_start:
	.res.b	H'1D0
__SCAREA_end:

	.end
;/*
;* Copyright (c) 2004 RENESAS TECHNOLOGY CORP. All Rights Reserved.
;* and RENESAS SOLUTIONS CORP. All Rights Reserved.
;*/