eit_entry.s

T-monitor监控程序

;/*""FILE COMMENT""*************************************************************
;*       System Name : RENESAS T-Engine/micro T-Engine
;*       File Name   : eit_entry.c
;*       Version     : 1.00.00
;*       Contents    : T-Kernel command functions
;*       Model       : SH7145 micro T-Engine
;*       CPU         : SH7145F
;*       Compiler    : Renesas SH-C
;*       OS          : T-Kernel
;*       note        : The Software is being delivered to you "AS IS" 
;*                   : and Renesas,whether explicitly or implicitly makes  
;*                   : no warranty as to its Use or performance. 
;*                   : RENESAS AND ITS SUPPLIER DO NOT AND CANNOT WARRANT 
;*                   : THE PERFORMANCE OR RESULTS YOU MAY OBTAIN  BY USING 
;*                   : THE SOFTWARE. AS TO ANY MATTER INCLUDING WITHOUT 
;*                   : LIMITATION NONINFRINGEMENT OF THIRD PARTY RIGHTS,
;*                   : MERCHANTABILITY, INTEGRATION, SATISFACTORY QUALITY, 
;*                   : OR FITNESS FOR ANY PARTICULAR PURPOSE.
;*
;*       Copyright (c) 2004 RENESAS TECHNOLOGY CORP. All Rights Reserved.
;*       AND RENESAS SOLUTIONS CORP. All Rights Reserved.
;*       history     : 2006.03.27 ver.1.00.00
;*""FILE COMMENT END""*********************************************************/

;/*
; *	Interrupt/EIT Entry
; */
EIT_VECTBL:	.equ	H'FFFFE000

	.macro INTENTRY NUM
	mov.l  r3,@-r15
	bra    IntHandlerChkVecNo
	mov    #\NUM,r3 ;/* delayed slot */

	.endm

	.macro INTHANDLER NUM
	mov.l  r3,@-r15
	mov.l  r2,@-r15
	mov.l  vectbladdr\NUM,r2
	mov.l  @r2,r2
	jmp    @r2
	mov    #\NUM,r3 ;/* delayed slot */

	.align 4
vectbladdr\NUM:	.data.l (EIT_VECTBL + (\NUM<<2))
	.endm

	.section HDR_P,code
NoHandler:
	rts
	nop

	.global TRAPHandler32,TRAPHandler33,TRAPHandler34,TRAPHandler35
	.global TRAPHandler36,TRAPHandler37
	.global IRQHandler0,IRQHandler1,IRQHandler2,IRQHandler3
	.global IRQHandler4,IRQHandler5,IRQHandler6,IRQHandler7

TRAPHandler32: ;/* T-Monitor service call */
	INTHANDLER 8 
TRAPHandler33: ;/* reserved */
	INTHANDLER 9
TRAPHandler34: ;/* T-Kernel system call */
	INTHANDLER 10
TRAPHandler35: ;/* T-Kernel tk_ret_int */
	INTHANDLER 11
TRAPHandler36: ;/* T-Kernel task dispatcher */
	INTHANDLER 12
TRAPHandler37: ;/* T-Kernel Debugger support */
	INTHANDLER 13

IRQHandler0:   ;/* IRQ0      VecNo.64,IntNo.40 */
	INTHANDLER 40 
IRQHandler1:   ;/* IRQ1      VecNo.65,IntNo.41 */
	INTHANDLER 41 
IRQHandler2:   ;/* IRQ2      VecNo.66,IntNo.42 */
	INTHANDLER 42 
IRQHandler3:   ;/* IRQ3      VecNo.67,IntNo.43 */
	INTHANDLER 43 
IRQHandler4:   ;/* IRQ4      VecNo.68,IntNo.44 */
	INTHANDLER 44 
IRQHandler5:   ;/* IRQ5      VecNo.69,IntNo.45 */
	INTHANDLER 45 
IRQHandler6:   ;/* IRQ6      VecNo.70,IntNo.46 */
	INTHANDLER 46 
IRQHandler7:   ;/* IRQ7      VecNo.71,IntNo.47 */
	INTHANDLER 47 

	.section HDR2_P,code
IntHandlerChkVecNo:
	mov.l  r2,@-r15
	mov.l  r0,@-r15
	mov.l  IntHdrVecTblAddr,r2
	mov    r3,r0
	shll2  r0
	add    r0,r2
	mov.l  @r2,r2
	mov.l  @r15+,r0 ;/* delayed slot */
	jmp    @r2
	nop    ;/* delayed slot */

	.align 4
IntHdrVecTblAddr:	.data.l EIT_VECTBL

IntHandlerEntry4:  ;/* ippan hutou meirei */
	INTENTRY 2
IntHandlerEntry6:  ;/* slot hutou meirei */
	INTENTRY 3
IntHandlerEntry9:  ;/* CPU address error */
	INTENTRY 4
IntHandlerEntry10:  ;/* DMA address error */
	INTENTRY 5
IntHandlerEntry11:  ;/* NMI */
	INTENTRY 6
InthandlerEntry12:  ;/* user break */
	INTENTRY 7
IntHandlerEntry38:  ;/* TRAPA #38 IntNo.14 */
	INTENTRY 14
IntHandlerEntry39:  ;/* TRAPA #39 IntNo.15 */
	INTENTRY 15
IntHandlerEntry40:  ;/* TRAPA #40 IntNo.16 */
	INTENTRY 16
IntHandlerEntry41:  ;/* TRAPA #41 IntNo.17 */
	INTENTRY 17
IntHandlerEntry42:  ;/* TRAPA #42 IntNo.18 */
	INTENTRY 18
IntHandlerEntry43:  ;/* TRAPA #43 IntNo.19 */
	INTENTRY 19
IntHandlerEntry44:  ;/* TRAPA #44 IntNo.20 */
	INTENTRY 20
IntHandlerEntry45:  ;/* TRAPA #45 IntNo.21 */
	INTENTRY 21
IntHandlerEntry46:  ;/* TRAPA #46 IntNo.22 */
	INTENTRY 22
IntHandlerEntry47:  ;/* TRAPA #47 IntNo.23 */
	INTENTRY 23
IntHandlerEntry48:  ;/* TRAPA #48 IntNo.24 */
	INTENTRY 24
IntHandlerEntry49:  ;/* TRAPA #49 IntNo.25 */
	INTENTRY 25
IntHandlerEntry50:  ;/* TRAPA #50 IntNo.26 */
	INTENTRY 26
IntHandlerEntry51:  ;/* TRAPA #51 IntNo.27 */
	INTENTRY 27
IntHandlerEntry52:  ;/* TRAPA #52 IntNo.28 */
	INTENTRY 28
IntHandlerEntry53:  ;/* TRAPA #53 IntNo.29 */
	INTENTRY 29
IntHandlerEntry54:  ;/* TRAPA #54 IntNo.30 */
	INTENTRY 30
IntHandlerEntry55:  ;/* TRAPA #55 IntNo.31 */
	INTENTRY 31
IntHandlerEntry56:  ;/* TRAPA #56 IntNo.32 */
	INTENTRY 32
IntHandlerEntry57:  ;/* TRAPA #57 IntNo.33 */
	INTENTRY 33
IntHandlerEntry58:  ;/* TRAPA #58 IntNo.34 */
	INTENTRY 34
IntHandlerEntry59:  ;/* TRAPA #59 IntNo.35 */
	INTENTRY 35
IntHandlerEntry60:  ;/* TRAPA #60 IntNo.36 */
	INTENTRY 36
IntHandlerEntry61:  ;/* TRAPA #61 IntNo.37 */
	INTENTRY 37
IntHandlerEntry62:  ;/* TRAPA #62 IntNo.38 */
	INTENTRY 38
IntHandlerEntry63:  ;/* TRAPA #63 IntNo.39 */
	INTENTRY 39
IntHandlerEntry72:  ;/* DMA(DEI0) VecNo.72,IntNo.48 */
	INTENTRY 48
IntHandlerEntry76:  ;/* DMA(DEI1) VecNo.76,IntNo.49 */
	INTENTRY 49
IntHandlerEntry80:  ;/* DMA(DEI2) VecNo.80,IntNo.50 */
	INTENTRY 50
IntHandlerEntry84:  ;/* DMA(DEI3) VecNo.84,IntNo.51 */
	INTENTRY 51
IntHandlerEntry88:  ;/* MTU0(TGIA0) VecNo.88,IntNo.52 */
	INTENTRY 52
IntHandlerEntry89:  ;/* MTU0(TGIB0) VecNo.89,IntNo.53 */
	INTENTRY 53
IntHandlerEntry90:  ;/* MTU0(TGIC0) VecNo.90,IntNo.54 */
	INTENTRY 54
IntHandlerEntry91:  ;/* MTU0(TGID0) VecNo.91,IntNo.55 */
	INTENTRY 55
IntHandlerEntry92:  ;/* MTU0(TCIV0) VecNo.92,IntNo.56 */
	INTENTRY 56
IntHandlerEntry96:  ;/* MTU1(TGIA1) VecNo.96,IntNo.57 */
	INTENTRY 57
IntHandlerEntry97:  ;/* MTU1(TGIB1) VecNo.97,IntNo.58 */
	INTENTRY 58
IntHandlerEntry100:  ;/* MTU1(TCIV1) VecNo.100,IntNo.59 */
	INTENTRY 59
IntHandlerEntry101:  ;/* MTU1(TCIU1) VecNo.101,IntNo.60 */
	INTENTRY 60
IntHandlerEntry104:  ;/* MTU2(TGIA2) VecNo.104,IntNo.61 */
	INTENTRY 61
IntHandlerEntry105:  ;/* MTU2(TGIB2) VecNo.105,IntNo.62 */
	INTENTRY 62
IntHandlerEntry108:  ;/* MTU2(TCIV2) VecNo.108,IntNo.63 */
	INTENTRY 63
IntHandlerEntry109:  ;/* MTU2(TCIU2) VecNo.109,IntNo.64 */
	INTENTRY 64
IntHandlerEntry112:  ;/* MTU3(TGIA3) VecNo.112,IntNo.65 */
	INTENTRY 65
IntHandlerEntry113:  ;/* MTU3(TGIB3) VecNo.113,IntNo.66 */
	INTENTRY 66
IntHandlerEntry114:  ;/* MTU3(TGIC3) VecNo.114,IntNo.67 */
	INTENTRY 67
IntHandlerEntry115:  ;/* MTU3(TGID3) VecNo.115,IntNo.68 */
	INTENTRY 68
IntHandlerEntry116:  ;/* MTU3(TCIV3) VecNo.116,IntNo.69 */
	INTENTRY 69
IntHandlerEntry120:  ;/* MTU4(TGIA4) VecNo.120,IntNo.70 */
	INTENTRY 70
IntHandlerEntry121:  ;/* MTU4(TGIB4) VecNo.121,IntNo.71 */
	INTENTRY 71
IntHandlerEntry122:  ;/* MTU4(TGIC4) VecNo.122,IntNo.72 */
	INTENTRY 72
IntHandlerEntry123:  ;/* MTU4(TGID4) VecNo.123,IntNo.73 */
	INTENTRY 73
IntHandlerEntry124:  ;/* MTU4(TCIV4) VecNo.124,IntNo.74 */
	INTENTRY 74
IntHandlerEntry128:  ;/* SCI0(ERI0) VecNo.128,IntNo.75 */
	INTENTRY 75
IntHandlerEntry129:  ;/* SCI0(RXI0) VecNo.129,IntNo.76 */
	INTENTRY 76
IntHandlerEntry130:  ;/* SCI0(TXI0) VecNo.130,IntNo.77 */
	INTENTRY 77
IntHandlerEntry131:  ;/* SCI0(TEI0) VecNo.131,IntNo.78 */
	INTENTRY 78
IntHandlerEntry132:  ;/* SCI1(ERI1) VecNo.132,IntNo.79 */