dm9008_8bit_mode.c

dm9008_8bit_mode_linux2.4 driver

	u8 reg_save;
	
	
//	DMFE_DBUG(0, "dmfe_timer()", 0);
	
	/* Save previous register address */
	reg_save = dmfe_inb(db->io_addr);
	
	/* TX timeout check  add by dd */
/*
	if (dev->trans_start&&((jiffies-dev->trans_start)>DMFE_TX_TIMEOUT)) {
		db->device_wait_reset = 1;
		db->reset_tx_timeout++;
	} 
*/	
	/* dynamic RESET check and do */
	if (db->device_wait_reset) {
		netif_stop_queue(dev); 
		db->reset_counter++;
		db->device_wait_reset = 0;
		dev->trans_start = 0;
		dmfe_init_dm9000(dev);
		netif_wake_queue(dev);
	}
	
	/* Restore previous register address */
	dmfe_outb(reg_save, db->io_addr);
	
	/* Set timer again */
	db->timer.expires = DMFE_TIMER_WUT;
	add_timer(&db->timer);

}

#if !defined(CHECKSUM)
#define check_rx_ready(a)	((a)&0x01)
#else
inline u8 check_rx_ready(u8 rxbyte)
{
	if (!(rxbyte & 0x01))
		return 0;
	return ((rxbyte >> 4) | 0x01);
}
#endif

/*
  Received a packet and pass to upper layer
*/
// make sure test fun not used ,set by dd 06.08.25
//if(0)
//static void dmfe_packet_receive(struct net_device *dev)
//{
//	printk("get packet \n");
//	dev = dmfe_dev;
//	board_info_t *db = (board_info_t *)dev->priv;
//	struct sk_buff *skb;
//	u8 rxbyte, val;
//	u16 i, GoodPacket; 
//	u16 tmplen = 0;
//
//	rx_t rx;
//// 	modi by dd ,06.08.19
////	DATA_TYPE * ptr = (DATA_TYPE*)℞
//	u8 * ptr=(u8 *)℞
////	DATA_TYPE *rdptr;
//	u8 *rdptr;
////	DMFE_DBUG(0, "dmfe_packet_receive()", 0);
//
//	do {
//		ior(db, 0xf0);			/* Dummy read */
//		rxbyte = dmfe_inb(db->io_data);	/* Got most updated data */
//
//		/* packet ready to receive check */
//		if(!(val = check_rx_ready(rxbyte))) break;
//
//		/* A packet ready now  & Get status/length */
//		GoodPacket = TRUE;
//
//		dmfe_outb(0xf2, db->io_addr);
//
//		/* Read packet status & length */
////		for (i = 0; i < 4 / IO_MODE; i++)
////		for (i = 0; i < 4 / 4; i++)
////			*(ptr+i) = VALIN(db->io_data);
//		//add by dd ,06,08,19
////		*ptr=dmfe_inb(db->io_data)+(dmfe_inb(db->io_data)<<8);
//
////		*(ptr+i) = dmfe_inb(db->io_data)+(dmfe_inb(db->io_data)<<8);
//		*(ptr+i)= dmfe_inb(db->io_data);
//
//		/* Packet status check */
//		if (rx.desc.status & 0xbf)
//		{
//			GoodPacket = FALSE;
//			if (rx.desc.status & 0x01) 
//			{
//				db->stats.rx_fifo_errors++;
//				printk("<RX FIFO error>\n");
//			}
//			if (rx.desc.status & 0x02) 
//			{
//				db->stats.rx_crc_errors++;
//				printk("<RX CRC error>\n");
//			}
//			if (rx.desc.status & 0x80) 
//			{
//				db->stats.rx_length_errors++;
//				printk("<RX Length error>\n");
//			}
//			if (rx.desc.status & 0x08)
//				printk("<Physical Layer error>\n");
//		}
//
//		/* Move data from MIC */
//		if (db->device_wait_reset) break;
//
//		if (!GoodPacket || (!(skb = dev_alloc_skb(rx.desc.length+4))))
//		{
//			/* Without buffer or error packet */
//			printk("<Without buffer or packet error>\n");
////			for (i = 0; i < tmplen; i++)
//			for (i= 0;i< rx.desc.length;i++)
////				VALIN(db->io_data);
//				dmfe_inb(db->io_data);
//			continue;
//		}
//
//		skb->dev = dev;
//		skb_reserve(skb, 2);
//		rdptr = (u8 *)skb_put(skb, rx.desc.length - 4);
//
//
//			
//		/* Read received packet from RX SARM */
////		tmplen = (rx.desc.length + IO_MODE-1) / IO_MODE; // modi by dd
////		tmplen = (rx.desc.length + 4-1) / 4;
////		for ( i = 0 ; i < tmplen; i++)
//		for ( i=0;i<rx.desc.length;i++)
////			(rdptr)[i]=VALIN(db->io_data);
//			(rdptr)[i]=dmfe_inb(db->io_data);			
//		/* Pass to upper layer */
//		skb->protocol = eth_type_trans(skb,dev);
////#if defined(CHECKSUM)
////		if (val == 0x01)
////			(struct sk_buff*)skb->ip_summed = CHECKSUM_UNNECESSARY;
////#endif
//		netif_rx(skb);
//		db->stats.rx_packets++;
//		db->stats.rx_bytes += rx.desc.length;
////add by dd .06.08.19
////		db->last_rx=jiffies;
////		db->cont_rx_pkt_cnt++;
////		if(db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT)
////		{
////		dmfe_tx_done(0);
////		break;
////		}
////
//	}while(rxbyte == DM9KS_PKT_RDY);
//	
//}
//endif
static void dmfe_packet_receive(struct net_device *dev)
{
	dev = dmfe_dev;
	board_info_t *db = (board_info_t *)dev->priv;
	struct sk_buff *skb;
	u8 rxbyte, val;
	u16 i, GoodPacket, tmplen = 0;

	rx_t rx;

	DATA_TYPE * ptr = (DATA_TYPE*)&rx;
	DATA_TYPE *rdptr;

	DMFE_DBUG(0, "dmfe_packet_receive()", 0);

	do {
		ior(db, 0xf0);			/* Dummy read */
		rxbyte = dmfe_inb(db->io_data);	/* Got most updated data */

		/* packet ready to receive check */
		if(!(val = check_rx_ready(rxbyte))) break;

		/* A packet ready now  & Get status/length */
		GoodPacket = TRUE;
		dmfe_outb(0xf2, db->io_addr);

		/* Read packet status & length */
//		for (i = 0; i < 4 / IO_MODE; i++)
		for (i = 0; i < 4 ; i++)
			*(ptr+i) = dmfe_inb(db->io_data);

		/* Packet status check */
		if (rx.desc.status & 0xbf)
		{
			GoodPacket = FALSE;
			if (rx.desc.status & 0x01) 
			{
				db->stats.rx_fifo_errors++;
				printk("<RX FIFO error>\n");
			}
			if (rx.desc.status & 0x02) 
			{
				db->stats.rx_crc_errors++;
				printk("<RX CRC error>\n");
			}
			if (rx.desc.status & 0x80) 
			{
				db->stats.rx_length_errors++;
				printk("<RX Length error>\n");
			}
			if (rx.desc.status & 0x08)
				printk("<Physical Layer error>\n");
		}

		/* Move data from MIC */
		if (db->device_wait_reset) break;

		if (!GoodPacket || (!(skb = dev_alloc_skb(rx.desc.length+4))))
		{
			/* Without buffer or error packet */
			printk("<Without buffer or packet error>\n");
			for (i = 0; i < tmplen; i++)
				dmfe_inb(db->io_data);
			continue;
		}

		skb->dev = dev;
		skb_reserve(skb, 2);
		rdptr = (DATA_TYPE *)skb_put(skb, rx.desc.length - 4);
			
		/* Read received packet from RX SARM */
//		tmplen = (rx.desc.length + IO_MODE-1) / IO_MODE; // modi by dd
		tmplen = (rx.desc.length + 1-1) / 1;
		for ( i = 0 ; i < tmplen; i++)
			(rdptr)[i]=dmfe_inb(db->io_data);
				
		/* Pass to upper layer */
		skb->protocol = eth_type_trans(skb,dev);
//#if defined(CHECKSUM)
//		if (val == 0x01)
//			(struct sk_buff*)skb->ip_summed = CHECKSUM_UNNECESSARY;
//#endif
		netif_rx(skb);
		db->stats.rx_packets++;
		db->stats.rx_bytes += rx.desc.length;
			
	}while(rxbyte == DM9KS_PKT_RDY);
	
}
/*
  Read a word data from SROM ,Because we don't have SROM ,so Delete that 
*/
//static u16 read_srom_word(board_info_t *db, int offset)
//{
//	iow(db, 0xc, offset);
//	iow(db, 0xb, 0x4);
//	udelay(200);
//	iow(db, 0xb, 0x0);
//	return (ior(db, 0xd) + (ior(db, 0xe) << 8) );
//}

/*
  Set MIC multicast address
*/
static void dm9000_hash_table(struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;
	struct dev_mc_list *mcptr = dev->mc_list;
	int mc_cnt = dev->mc_count;
	u32 hash_val;
	u16 i, oft, hash_table[4];

//	DMFE_DBUG(0, "dm9000_hash_table()", 0);

	/* Set Node address */
	for (i = 0, oft = 0x10; i < 6; i++, oft++)
		iow(db, oft, mac[i]);
//        memcpy(dev->dev_addr,mac,dev->addr_len);
	/* Clear Hash Table */
	for (i = 0; i < 4; i++)
		hash_table[i] = 0x0;
	/* broadcast address */
	hash_table[3] = 0x8000;

	/* the multicast address in Hash Table : 64 bits */
/*
	for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
		hash_val = cal_CRC((char *)mcptr->dmi_addr, 6, 0) & 0x3f; 
		hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
	}
*/
	/* Write the hash table to MAC MD table */
	for (i = 0, oft = 0x16; i < 4; i++) {
		iow(db, oft++, hash_table[i] & 0xff);
		iow(db, oft++, (hash_table[i] >> 8) & 0xff);
	}

}

/*
  Calculate the CRC valude of the Rx packet
  flag = 1 : return the reverse CRC (for the received packet CRC)
         0 : return the normal CRC (for Hash Table index)
*/
static unsigned long cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
{
	
	u32 crc = ether_crc_le(Len, Data);

	if (flag) 
		return ~crc;
		
	return crc;
	 
}

/*
   Read a byte from I/O port modi by dd 
*/
//add by dd ,06.08.12
static void dmfe_outb(u8 data ,u32 b4addr)
{
	*((u8 *)b4addr) = data;
}
static u8 dmfe_inb(u32 b4addr)
{
	u8 brtn;
	brtn=*(u8 *)b4addr;
	return (brtn);

}
//


//modi by dd at same time 
static u8 ior(board_info_t *db, int reg)
{
	int i;
	dmfe_outb(reg, db->io_addr);
	for(i=0;i<200;i++)
	{
	}
	return ((u16) dmfe_inb(db->io_data));
}

/*
   Write a byte to I/O port  modi by dd 
*/
static void iow(board_info_t *db, int reg, u8 value)
{
	int i;
	dmfe_outb(reg, db->io_addr);
	for(i=0;i<200;i++)
	{
	}
	dmfe_outb(value, db->io_data);
}

/*
   Read a word from phyxcer 
*/

static u16 phy_read(board_info_t *db, int reg)
{
	/* Fill the phyxcer register into REG_0C */
	iow(db, 0xc, DM9KS_PHY | reg);

	iow(db, 0xb, 0xc); 	/* Issue phyxcer read command */
	udelay(100);		/* Wait read complete */
	iow(db, 0xb, 0x0); 	/* Clear phyxcer read command */

	/* The read data keeps on REG_0D & REG_0E */
	return ( ior(db, 0xe) << 8 ) | ior(db, 0xd);
}

/*
   Write a word to phyxcer
*/
static void phy_write(board_info_t *db, int reg, u16 value)
{
	/* Fill the phyxcer register into REG_0C */
	iow(db, 0xc, DM9KS_PHY | reg);

	/* Fill the written data into REG_0D & REG_0E */
	iow(db, 0xd, (value & 0xff));
	iow(db, 0xe, ( (value >> 8) & 0xff));
					
	iow(db, 0xb, 0xa);		/* Issue phyxcer write command */
	udelay(500);			/* Wait write complete */
	iow(db, 0xb, 0x0);		/* Clear phyxcer write command */
}

#ifdef MODULE

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Dongliang ,KAIDA ");
MODULE_DESCRIPTION(" ISA/uP Fast Ethernet Driver");
MODULE_PARM(debug, "i");
//MODULE_PARM(mode, "i");

/* Description: 
   when user used insmod to add module, system invoked init_module()
   to initilize and register.
*/
int init_module(void)
{
//	DMFE_DBUG(0, "init_module() ", debug);

	if (debug) 
		dmfe_debug = debug;   /* set debug flag */

//	switch(mode) {
//		case DM9KS_10MHD:
//		case DM9KS_100MHD:
//		case DM9KS_10MFD:
//		case DM9KS_100MFD:
//			media_mode = mode;
//			break;
//		default:
//			media_mode = DM9KS_AUTO;
//	}

	return dmfe_probe(0);              /* search board and register */
}

/* Description: 
   when user used rmmod to delete module, system invoked clean_module()
   to  un-register DEVICE.
*/
/* add module set by dd */

void cleanup_module(void)

{
	board_info_t * db;
//	DMFE_DBUG(0, "clean_module()", 0);

	unregister_netdev(dmfe_dev);
	db = (board_info_t *)dmfe_dev->priv;
	release_region(dmfe_dev->base_addr, 2);
	kfree(db);		/* free board information */
	kfree(dmfe_dev);	/* free device structure */
	
//	DMFE_DBUG(0, "clean_module() exit", 0);
}
#endif