📄 custom.c
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/*
(c) Copyright SGS-Thomson Microelectronics Limited 1999.
File: mico.c
Author: Lionel Prats
Original Work: Lehu, THT RAJAN (OSLINK version)
P. LEY (DCU VERSION for INTEL's chips)
Description:
Library routines for the M29F400T/B 4Mbit (512k*8) Flash memories.
Supports AMD/ST Flash devices (29F400T, 29F400B, 29W800T, 29W800B) only.
Modifications:
Date b Modification Initials
---- ------------ --------
08-09-00 Optimization BK
05-08-00 Added 16Mbit 1-chip Flash TM
28-06-99 Added 2-chip memory support LP
20-06-99 Added memory structure for 8mbit EPROM LP
15-06-99 Added TOP/BOT support LP
11-06-99 Creation v0.1 LP
******************************************************************************/
#include <ktcable.h>
#include <task.h>
#include "stflashd.h"
#include "stlite.h" /* os20 for standard definitions, */
#define MFR_ID_AMD 0x0001 /* AMD mfr_id */
#define DEV_ID_M29F400T 0x00D5 /* ST 29F400T dev_id */
#define DEV_ID_M29F400B 0x00D6 /* ST 29F400B dev_id */
#define DEV_ID_M29W800T 0x00D7 /* ST 29W800T dev_id */
#define DEV_ID_M29W800B 0x005B /* ST 29W800B dev_id */
#define DEV_ID_AM29F400T 0x2223 /* AMD 29F400T dev_id */
#define DEV_ID_AM29F400B 0x22AB /* AMD 29F400B dev_id */
#define DEV_ID_M29W160BT 0x22c4 /* ST 29W160BT dev_id */
#define DEV_ID_M29W160BB 0x2249 /* ST 29W160BB dev_id */
#define DEV_ID_AM29F160T 0x22c4 /* AMD 29F160T dev_id */
#define DEV_ID_AM29F160B 0x2249 /* AMD 29F160B dev_id */
//#define DEV_ID_SST39VF3201 0x235B
#define DEV_ID_M29W320DT 0x22CA
#define OPTIMIZATION_ENABLED
char Chip_selected = 1;
/* =============================FlashROM block defines========================= */
#define FROM_BOT 0x7fc00000 /* bot_most 16Mbit FROM address */
/* =============================FlashROM blocks TL-version===================== */
#define FLASH_1_BASE 0x7fc00000
#define BLOCK_0 (FLASH_1_BASE) /* BLOCK_0 - 32 KWORD */
#define BLOCK_1 (FLASH_1_BASE | 0x010000) /* BLOCK_1 - 32 KWORD */
#define BLOCK_2 (FLASH_1_BASE | 0x020000) /* BLOCK_2 - 32 KWORD */
#define BLOCK_3 (FLASH_1_BASE | 0x030000) /* BLOCK_3 - 32 KWORD */
#define BLOCK_4 (FLASH_1_BASE | 0x040000) /* BLOCK_4 - 32 KWORD */
#define BLOCK_5 (FLASH_1_BASE | 0x050000) /* BLOCK_5 - 32 KWORD */
#define BLOCK_6 (FLASH_1_BASE | 0x060000) /* BLOCK_6 - 32 KWORD */
#define BLOCK_7 (FLASH_1_BASE | 0x070000) /* BLOCK_7 - 32 KWORD */
#define BLOCK_8 (FLASH_1_BASE | 0x080000) /* BLOCK_8 - 32 KWORD */
#define BLOCK_9 (FLASH_1_BASE | 0x090000) /* BLOCK_9 - 32 KWORD */
#define BLOCK_10 (FLASH_1_BASE | 0x0a0000) /* BLOCK_10 - 32 KWORD */
#define BLOCK_11 (FLASH_1_BASE | 0x0b0000) /* BLOCK_11 - 32 KWORD */
#define BLOCK_12 (FLASH_1_BASE | 0x0c0000) /* BLOCK_12 - 32 KWORD */
#define BLOCK_13 (FLASH_1_BASE | 0x0d0000) /* BLOCK_13 - 32 KWORD */
#define BLOCK_14 (FLASH_1_BASE | 0x0e0000) /* BLOCK_14 - 32 KWORD */
#define BLOCK_15 (FLASH_1_BASE | 0x0f0000) /* BLOCK_15 - 32 KWORD */
#define BLOCK_16 (FLASH_1_BASE | 0x100000) /* BLOCK_16 - 32 KWORD */
#define BLOCK_17 (FLASH_1_BASE | 0x110000) /* BLOCK_17 - 32 KWORD */
#define BLOCK_18 (FLASH_1_BASE | 0x120000) /* BLOCK_18 - 32 KWORD */
#define BLOCK_19 (FLASH_1_BASE | 0x130000) /* BLOCK_19 - 32 KWORD */
#define BLOCK_20 (FLASH_1_BASE | 0x140000) /* BLOCK_20 - 32 KWORD */
#define BLOCK_21 (FLASH_1_BASE | 0x150000) /* BLOCK_21 - 32 KWORD */
#define BLOCK_22 (FLASH_1_BASE | 0x160000) /* BLOCK_22 - 32 KWORD */
#define BLOCK_23 (FLASH_1_BASE | 0x170000) /* BLOCK_23 - 32 KWORD */
#define BLOCK_24 (FLASH_1_BASE | 0x180000) /* BLOCK_24 - 32 KWORD */
#define BLOCK_25 (FLASH_1_BASE | 0x190000) /* BLOCK_25 - 32 KWORD */
#define BLOCK_26 (FLASH_1_BASE | 0x1a0000) /* BLOCK_26 - 32 KWORD */
#define BLOCK_27 (FLASH_1_BASE | 0x1b0000) /* BLOCK_27 - 32 KWORD */
#define BLOCK_28 (FLASH_1_BASE | 0x1c0000) /* BLOCK_28 - 32 KWORD */
#define BLOCK_29 (FLASH_1_BASE | 0x1d0000) /* BLOCK_29 - 32 KWORD */
#define BLOCK_30 (FLASH_1_BASE | 0x1e0000) /* BLOCK_30 - 32 KWORD */
#define BLOCK_31 (FLASH_1_BASE | 0x1f0000) /* BLOCK_31 - 16 KWORD */
/*other 2 m bit*/
#define BLOCK_32 (FLASH_1_BASE | 0x200000) /* BLOCK_22 - 32 KWORD */
#define BLOCK_33 (FLASH_1_BASE | 0x210000) /* BLOCK_23 - 32 KWORD */
#define BLOCK_34 (FLASH_1_BASE | 0x220000) /* BLOCK_24 - 32 KWORD */
#define BLOCK_35 (FLASH_1_BASE | 0x230000) /* BLOCK_25 - 32 KWORD */
#define BLOCK_36 (FLASH_1_BASE | 0x240000) /* BLOCK_26 - 32 KWORD */
#define BLOCK_37 (FLASH_1_BASE | 0x250000) /* BLOCK_27 - 32 KWORD */
#define BLOCK_38 (FLASH_1_BASE | 0x260000) /* BLOCK_28 - 32 KWORD */
#define BLOCK_39 (FLASH_1_BASE | 0x270000) /* BLOCK_29 - 32 KWORD */
#define BLOCK_40 (FLASH_1_BASE | 0x280000) /* BLOCK_30 - 32 KWORD */
#define BLOCK_41 (FLASH_1_BASE | 0x290000) /* BLOCK_31 - 16 KWORD */
#define BLOCK_42 (FLASH_1_BASE | 0x2a0000) /* BLOCK_26 - 32 KWORD */
#define BLOCK_43 (FLASH_1_BASE | 0x2b0000) /* BLOCK_27 - 32 KWORD */
#define BLOCK_44 (FLASH_1_BASE | 0x2c0000) /* BLOCK_28 - 32 KWORD */
#define BLOCK_45 (FLASH_1_BASE | 0x2d0000) /* BLOCK_29 - 32 KWORD */
#define BLOCK_46 (FLASH_1_BASE | 0x2e0000) /* BLOCK_30 - 32 KWORD */
#define BLOCK_47 (FLASH_1_BASE | 0x2f0000) /* BLOCK_31 - 16 KWORD */
#define BLOCK_48 (FLASH_1_BASE | 0x300000) /* BLOCK_22 - 32 KWORD */
#define BLOCK_49 (FLASH_1_BASE | 0x310000) /* BLOCK_23 - 32 KWORD */
#define BLOCK_50 (FLASH_1_BASE | 0x320000) /* BLOCK_24 - 32 KWORD */
#define BLOCK_51 (FLASH_1_BASE | 0x330000) /* BLOCK_25 - 32 KWORD */
#define BLOCK_52 (FLASH_1_BASE | 0x340000) /* BLOCK_26 - 32 KWORD */
#define BLOCK_53 (FLASH_1_BASE | 0x350000) /* BLOCK_27 - 32 KWORD */
#define BLOCK_54 (FLASH_1_BASE | 0x360000) /* BLOCK_28 - 32 KWORD */
#define BLOCK_55 (FLASH_1_BASE | 0x370000) /* BLOCK_29 - 32 KWORD */
#define BLOCK_56 (FLASH_1_BASE | 0x380000) /* BLOCK_30 - 32 KWORD */
#define BLOCK_57 (FLASH_1_BASE | 0x390000) /* BLOCK_31 - 16 KWORD */
#define BLOCK_58 (FLASH_1_BASE | 0x3a0000) /* BLOCK_26 - 32 KWORD */
#define BLOCK_59 (FLASH_1_BASE | 0x3b0000) /* BLOCK_27 - 32 KWORD */
#define BLOCK_60 (FLASH_1_BASE | 0x3c0000) /* BLOCK_28 - 32 KWORD */
#define BLOCK_61 (FLASH_1_BASE | 0x3d0000) /* BLOCK_29 - 32 KWORD */
#define BLOCK_62 (FLASH_1_BASE | 0x3e0000) /* BLOCK_30 - 32 KWORD */
#define BLOCK_63 (FLASH_1_BASE | 0x3f0000) /*8k*/
#define BLOCK_64 (FLASH_1_BASE | 0x3f2000)
#define BLOCK_65 (FLASH_1_BASE | 0x3f4000)
#define BLOCK_66 (FLASH_1_BASE | 0x3f6000)
#define BLOCK_67 (FLASH_1_BASE | 0x3f8000)
#define BLOCK_68 (FLASH_1_BASE | 0x3fa000)
#define BLOCK_69 (FLASH_1_BASE | 0x3fc000)
#define BLOCK_70 (FLASH_1_BASE | 0x3fe000)
#define DEVID_ADDR 0x00002 /* device id address offset in 8-bit mode */
#define C_CCL1_ADDR 0xaaaa /* First Coded Cycle address */
#define C_CCL2_ADDR 0x5555 /* Second Coded Cycle address */
#define COMMAND_ADDR 0xaaaa /* Address used to enter */
#define READ_IDENT 0x9090 /* Read Electronic Signature */
#define MFGID_ADDR 0 /* manufacturers id address */
#define MFR_ID_ST 0x0020 /* STMicroelectronics mfr_id */
#define MFR_ID_SST 0x00BF
/* =============================FlashROM cui_commands defines================== */
#define ERASE_CONFIRM 0x1010 /* Chip Erase Confirm */
#define B_ERASE_CONFIRM 0x3030 /* Block Erase Resume/Confirm */
#define ERASE_SETUP 0x8080 /* Set-up Erase */
#define PROGRAM_SETUP 0xa0a0 /* Program */
#define ERASE_SUSPEND 0xb0b0 /* Erase Suspend */
#define CODEDCYCLE_1 0x0000aaaa /* First Coded Cycle Data */
#define CODEDCYCLE_2 0x00005555 /* Second Coded Cycle Data */
#define READ_ARRAY 0xf0f0 /* Read Array/Reset */
#define CLEAR_SREG 0x50 /* clear status_reg command */
#define READ_SREG 0x70 /* read status_reg command */
/* ============================= Macros defines ================== */
#define RESET_FLASH_1 (*((UINT16*)FLASH_1_BASE) = READ_ARRAY)
#pragma ST_device(device_U16_t)
typedef volatile unsigned short device_U16_t;
device_U16_t *ptr_to_b; /* block_pointer def'n */
int write_error = 0, verify_error = 0;
int FLASH_NWRITED = 0;
BOOL FLASH_ALLOW_READ = TRUE;
void InputCodedSequence(ULONG address)
{
ptr_to_b = (device_U16_t *) (address | C_CCL1_ADDR); /* pointer to 29F400T boot_block */
*ptr_to_b = (device_U16_t) CODEDCYCLE_1;
ptr_to_b = (device_U16_t *) (address | C_CCL2_ADDR); /* pointer to 29F400T boot_block */
*ptr_to_b = (device_U16_t) CODEDCYCLE_2;
}
STATUS EarseBootBlock(void)
{
int result = 1, id;
sysFlash->ID(sysFlash, (u32 *) &id);
/* write word to addressed location */
if ((id & 0xff) != (MFR_ID_SST & 0xff))
{
result = EraseBlock((unsigned short *) (FLASH_START_ADDR | 0x3f2000));
if (!result)
{
return result;
}
result = EraseBlock((unsigned short *) (FLASH_START_ADDR | 0x3f4000));
if (!result)
{
return result;
}
result = EraseBlock((unsigned short *) (FLASH_START_ADDR | 0x3f6000));
if (!result)
{
return result;
}
result = EraseBlock((unsigned short *) (FLASH_START_ADDR | 0x3f8000));
if (!result)
{
return result;
}
result = EraseBlock((unsigned short *) (FLASH_START_ADDR | 0x3fa000));
if (!result)
{
return result;
}
result = EraseBlock((unsigned short *) (FLASH_START_ADDR | 0x3fc000));
if (!result)
{
return result;
}
result = EraseBlock((unsigned short *) (FLASH_START_ADDR | 0x3fe000));
return result;
}
else
{
result = EraseBlock((unsigned short *) (FLASH_START_ADDR | 0x3f8000));
if (!result)
{
return result;
}
result = EraseBlock((unsigned short *) (FLASH_START_ADDR | 0x3fa000));
if (!result)
{
return result;
}
result = EraseBlock((unsigned short *) (FLASH_START_ADDR | 0x3fc000));
return result;
}
}
/*=======================================================================================*/
/* If OPTIMIZATION_ENABLED is not defined execute block erase*/
int EraseBlock(UINT16 *block) /*erase flashrom block */
{
UINT16 lastreading;
int eraseprogressing = 1, erasefailed = 1;
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