pd.tan.qmsg

using judgement on average power overflow or too small to implement the protection on amplifier

{ "Info" "ITDB_TH_RESULT" "vgactr:inst\|itemp\[3\] Iin\[3\] Iiclk -3.935 ns register " "Info: th for register \"vgactr:inst\|itemp\[3\]\" (data pin = \"Iin\[3\]\", clock pin = \"Iiclk\") is -3.935 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Iiclk destination 2.561 ns + Longest register " "Info: + Longest clock path from clock \"Iiclk\" to destination register is 2.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.016 ns) 1.016 ns Iiclk 1 CLK PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.016 ns) = 1.016 ns; Loc. = PIN_91; Fanout = 1; CLK Node = 'Iiclk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "" { Iiclk } "NODE_NAME" } "" } } { "pd.bdf" "" { Schematic "E:/emtl/vgactr/pd.bdf" { { 232 112 280 248 "Iiclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.128 ns) + CELL(0.000 ns) 1.144 ns Iiclk~clkctrl 2 COMB CLKCTRL_G6 222 " "Info: 2: + IC(0.128 ns) + CELL(0.000 ns) = 1.144 ns; Loc. = CLKCTRL_G6; Fanout = 222; COMB Node = 'Iiclk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "0.128 ns" { Iiclk Iiclk~clkctrl } "NODE_NAME" } "" } } { "pd.bdf" "" { Schematic "E:/emtl/vgactr/pd.bdf" { { 232 112 280 248 "Iiclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.815 ns) + CELL(0.602 ns) 2.561 ns vgactr:inst\|itemp\[3\] 3 REG LCFF_X21_Y8_N17 50 " "Info: 3: + IC(0.815 ns) + CELL(0.602 ns) = 2.561 ns; Loc. = LCFF_X21_Y8_N17; Fanout = 50; REG Node = 'vgactr:inst\|itemp\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "1.417 ns" { Iiclk~clkctrl vgactr:inst|itemp[3] } "NODE_NAME" } "" } } { "vgactr.vhd" "" { Text "E:/emtl/vgactr/vgactr.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.618 ns ( 63.18 % ) " "Info: Total cell delay = 1.618 ns ( 63.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.943 ns ( 36.82 % ) " "Info: Total interconnect delay = 0.943 ns ( 36.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "2.561 ns" { Iiclk Iiclk~clkctrl vgactr:inst|itemp[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.561 ns" { Iiclk Iiclk~combout Iiclk~clkctrl vgactr:inst|itemp[3] } { 0.000ns 0.000ns 0.128ns 0.815ns } { 0.000ns 1.016ns 0.000ns 0.602ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "vgactr.vhd" "" { Text "E:/emtl/vgactr/vgactr.vhd" 81 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.782 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns Iin\[3\] 1 PIN PIN_97 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_97; Fanout = 1; PIN Node = 'Iin\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "" { Iin[3] } "NODE_NA