pd.tan.qmsg

using judgement on average power overflow or too small to implement the protection on amplifier

{ "Info" "ITDB_FULL_TCO_RESULT" "Iiclk sUp vgactr:inst\|SUP 7.471 ns register " "Info: tco from clock \"Iiclk\" to destination pin \"sUp\" through register \"vgactr:inst\|SUP\" is 7.471 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Iiclk source 2.594 ns + Longest register " "Info: + Longest clock path from clock \"Iiclk\" to source register is 2.594 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.016 ns) 1.016 ns Iiclk 1 CLK PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.016 ns) = 1.016 ns; Loc. = PIN_91; Fanout = 1; CLK Node = 'Iiclk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "" { Iiclk } "NODE_NAME" } "" } } { "pd.bdf" "" { Schematic "E:/emtl/vgactr/pd.bdf" { { 232 112 280 248 "Iiclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.128 ns) + CELL(0.000 ns) 1.144 ns Iiclk~clkctrl 2 COMB CLKCTRL_G6 222 " "Info: 2: + IC(0.128 ns) + CELL(0.000 ns) = 1.144 ns; Loc. = CLKCTRL_G6; Fanout = 222; COMB Node = 'Iiclk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "0.128 ns" { Iiclk Iiclk~clkctrl } "NODE_NAME" } "" } } { "pd.bdf" "" { Schematic "E:/emtl/vgactr/pd.bdf" { { 232 112 280 248 "Iiclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.602 ns) 2.594 ns vgactr:inst\|SUP 3 REG LCFF_X23_Y2_N5 2 " "Info: 3: + IC(0.848 ns) + CELL(0.602 ns) = 2.594 ns; Loc. = LCFF_X23_Y2_N5; Fanout = 2; REG Node = 'vgactr:inst\|SUP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "1.450 ns" { Iiclk~clkctrl vgactr:inst|SUP } "NODE_NAME" } "" } } { "vgactr.vhd" "" { Text "E:/emtl/vgactr/vgactr.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.618 ns ( 62.37 % ) " "Info: Total cell delay = 1.618 ns ( 62.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.976 ns ( 37.63 % ) " "Info: Total interconnect delay = 0.976 ns ( 37.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "2.594 ns" { Iiclk Iiclk~clkctrl vgactr:inst|SUP } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.594 ns" { Iiclk Iiclk~combout Iiclk~clkctrl vgactr:inst|SUP } { 0.000ns 0.000ns 0.128ns 0.848ns } { 0.000ns 1.016ns 0.000ns 0.602ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "vgactr.vhd" "" { Text "E:/emtl/vgactr/vgactr.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns + Longest register pin " "Info: + Longest register to pin delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vgactr:inst\|SUP 1 REG LCFF_X23_Y2_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y2_N5; Fanout = 2; REG Node = 'vgactr:inst\|SUP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "" { vgactr:inst|SUP } "NODE_NAME" } "" } } { "vgactr.vhd" "" { Text "E:/emtl/vgactr/vgactr.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.655 ns) + CELL(2.945 ns) 4.600 ns sUp 2 PIN PIN_72 0 " "Info: 2: + IC(1.655 ns) + CELL(2.945 ns) = 4.600 ns; Loc. = PIN_72; Fanout = 0; PIN Node = 'sUp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "4.600 ns" { vgactr:inst|SUP sUp } "NODE_NAME" } "" } } { "pd.bdf" "" { Schematic "E:/emtl/vgactr/pd.bdf" { { 232 512 688 248 "sUp" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.945 ns ( 64.02 % ) " "Info: Total cell delay = 2.945 ns ( 64.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.655 ns ( 35.98 % ) " "Info: Total interconnect delay = 1.655 ns ( 35.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "4.600 ns" { vgactr:inst|SUP sUp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.600 ns" { vgactr:inst|SUP sUp } { 0.000ns 1.655ns } { 0.000ns 2.945ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "2.594 ns" { Iiclk Iiclk~clkctrl vgactr:inst|SUP } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.594 ns" { Iiclk Iiclk~combout Iiclk~clkctrl vgactr:inst|SUP } { 0.000ns 0.000ns 0.128ns 0.848ns } { 0.000ns 1.016ns 0.000ns 0.602ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "4.600 ns" { vgactr:inst|SUP sUp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.600 ns" { vgactr:inst|SUP sUp } { 0.000ns 1.655ns } { 0.000ns 2.945ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Iiclk oclk 5.378 ns Longest " "Info: Longest tpd from source pin \"Iiclk\" to destination pin \"oclk\" is 5.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.016 ns) 1.016 ns Iiclk 1 CLK PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.016 ns) = 1.016 ns; Loc. = PIN_91; Fanout = 1; CLK Node = 'Iiclk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "" { Iiclk } "NODE_NAME" } "" } } { "pd.bdf" "" { Schematic "E:/emtl/vgactr/pd.bdf" { { 232 112 280 248 "Iiclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.128 ns) + CELL(0.000 ns) 1.144 ns Iiclk~clkctrl 2 COMB CLKCTRL_G6 222 " "Info: 2: + IC(0.128 ns) + CELL(0.000 ns) = 1.144 ns; Loc. = CLKCTRL_G6; Fanout = 222; COMB Node = 'Iiclk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "0.128 ns" { Iiclk Iiclk~clkctrl } "NODE_NAME" } "" } } { "pd.bdf" "" { Schematic "E:/emtl/vgactr/pd.bdf" { { 232 112 280 248 "Iiclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.268 ns) + CELL(2.966 ns) 5.378 ns oclk 3 PIN PIN_31 0 " "Info: 3: + IC(1.268 ns) + CELL(2.966 ns) = 5.378 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'oclk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "4.234 ns" { Iiclk~clkctrl oclk } "NODE_NAME" } "" } } { "pd.bdf" "" { Schematic "E:/emtl/vgactr/pd.bdf" { { 368 400 576 384 "oclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.982 ns ( 74.04 % ) " "Info: Total cell delay = 3.982 ns ( 74.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.396 ns ( 25.96 % ) " "Info: Total interconnect delay = 1.396 ns ( 25.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pd" "UNKNOWN" "V1" "E:/emtl/vgactr/db/pd.quartus_db" { Floorplan "E:/emtl/vgactr/" "" "5.378 ns" { Iiclk Iiclk~clkctrl oclk } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.378 ns" { Iiclk Iiclk~combout Iiclk~clkctrl oclk } { 0.000ns 0.000ns 0.128ns 1.268ns } { 0.000ns 1.016ns 0.000ns 2.966ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}