pd.map.qmsg

using judgement on average power overflow or too small to implement the protection on amplifier

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 02 11:39:15 2008 " "Info: Processing started: Sat Feb 02 11:39:15 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pd -c pd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pd -c pd" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vgactr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file vgactr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vgactr-rtl " "Info: Found design unit 1: vgactr-rtl" {  } { { "vgactr.vhd" "" { Text "E:/emtl/vgactr/vgactr.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 vgactr " "Info: Found entity 1: vgactr" {  } { { "vgactr.vhd" "" { Text "E:/emtl/vgactr/vgactr.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pd.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pd.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pd " "Info: Found entity 1: pd" {  } { { "pd.bdf" "" { Schematic "E:/emtl/vgactr/pd.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_iir.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file i2c_iir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_iir-ach " "Info: Found design unit 1: i2c_iir-ach" {  } { { "i2c_iir.vhd" "" { Text "E:/emtl/vgactr/i2c_iir.vhd" 24 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 i2c_iir " "Info: Found entity 1: i2c_iir" {  } { { "i2c_iir.vhd" "" { Text "E:/emtl/vgactr/i2c_iir.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_fir.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file i2c_fir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_fir-ach " "Info: Found design unit 1: i2c_fir-ach" {  } { { "i2c_fir.vhd" "" { Text "E:/emtl/vgactr/i2c_fir.vhd" 24 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 i2c_fir " "Info: Found entity 1: i2c_fir" {  } { { "i2c_fir.vhd" "" { Text "E:/emtl/vgactr/i2c_fir.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/emtl/vgactr/i2c_up.vhd " "Warning: Can't analyze file -- file E:/emtl/vgactr/i2c_up.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/emtl/vgactr/i2c_lw.vhd " "Warning: Can't analyze file -- file E:/emtl/vgactr/i2c_lw.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pd " "Info: Elaborating entity \"pd\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vgactr vgactr:inst " "Info: Elaborating entity \"vgactr\" for hierarchy \"vgactr:inst\"" {  } { { "pd.bdf" "inst" { Schematic "E:/emtl/vgactr/pd.bdf" { { 208 328 488 304 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" 281 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult vgactr:inst\|lpm_mult:I_square " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"vgactr:inst\|lpm_mult:I_square\"" {  } { { "vgactr.vhd" "I_square" { Text "E:/emtl/vgactr/vgactr.vhd" 96 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_ptr.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_ptr.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_ptr " "Info: Found entity 1: mult_ptr" {  } { { "db/mult_ptr.tdf" "" { Text "E:/emtl/vgactr/db/mult_ptr.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_ptr vgactr:inst\|lpm_mult:I_square\|mult_ptr:auto_generated " "Info: Elaborating entity \"mult_ptr\" for hierarchy \"vgactr:inst\|lpm_mult:I_square\|mult_ptr:auto_generated\"" {  } { { "lpm_mult.tdf" "auto_generated" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" 372 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub vgactr:inst\|lpm_add_sub:square_sum " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"vgactr:inst\|lpm_add_sub:square_sum\"" {  } { { "vgactr.vhd" "square_sum" { Text "E:/emtl/vgactr/vgactr.vhd" 138 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_5pe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_5pe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_5pe " "Info: Found entity 1: add_sub_5pe" {  } { { "db/add_sub_5pe.tdf" "" { Text "E:/emtl/vgactr/db/add_sub_5pe.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_5pe vgactr:inst\|lpm_add_sub:square_sum\|add_sub_5pe:auto_generated " "Info: Elaborating entity \"add_sub_5pe\" for hierarchy \"vgactr:inst\|lpm_add_sub:square_sum\|add_sub_5pe:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 117 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 254 " "Info: Resynthesizing 0 WYSIWYG logic cells and I/Os using \"balanced\" technology mapper which leaves 254 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 0 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "346 " "Info: Implemented 346 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "29 " "Info: Implemented 29 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "309 " "Info: Implemented 309 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_DSP_ELEM" "4 " "Info: Implemented 4 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 02 11:39:20 2008 " "Info: Processing ended: Sat Feb 02 11:39:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}