📄 pd.map.rpt
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; LPM_WIDTHS ; 1 ; Integer ;
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LATENCY ; 0 ; Untyped ;
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
; USE_EAB ; OFF ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY ; YES ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; CBXI_PARAMETER ; mult_ptr ; Untyped ;
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
+------------------------------------------------+------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: vgactr:inst|lpm_add_sub:square_sum ;
+------------------------+-------------+------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+------------------------------------------+
; LPM_WIDTH ; 28 ; Integer ;
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_5pe ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance ;
+---------------------------------------+-------------------------------+
; Name ; Value ;
+---------------------------------------+-------------------------------+
; Number of entity instances ; 2 ;
; Entity Instance ; vgactr:inst|lpm_mult:I_square ;
; -- LPM_WIDTHA ; 14 ;
; -- LPM_WIDTHB ; 14 ;
; -- LPM_WIDTHP ; 28 ;
; -- LPM_REPRESENTATION ; SIGNED ;
; -- INPUT_A_IS_CONSTANT ; NO ;
; -- INPUT_B_IS_CONSTANT ; NO ;
; -- USE_EAB ; OFF ;
; -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES ;
; -- INPUT_A_FIXED_VALUE ; Bx ;
; -- INPUT_B_FIXED_VALUE ; Bx ;
; Entity Instance ; vgactr:inst|lpm_mult:Q_square ;
; -- LPM_WIDTHA ; 14 ;
; -- LPM_WIDTHB ; 14 ;
; -- LPM_WIDTHP ; 28 ;
; -- LPM_REPRESENTATION ; SIGNED ;
; -- INPUT_A_IS_CONSTANT ; NO ;
; -- INPUT_B_IS_CONSTANT ; NO ;
; -- USE_EAB ; OFF ;
; -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES ;
; -- INPUT_A_FIXED_VALUE ; Bx ;
; -- INPUT_B_FIXED_VALUE ; Bx ;
+---------------------------------------+-------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/emtl/vgactr/pd.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Sat Feb 02 11:39:15 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pd -c pd
Info: Found 2 design units, including 1 entities, in source file vgactr.vhd
Info: Found design unit 1: vgactr-rtl
Info: Found entity 1: vgactr
Info: Found 1 design units, including 1 entities, in source file pd.bdf
Info: Found entity 1: pd
Info: Found 2 design units, including 1 entities, in source file i2c_iir.vhd
Info: Found design unit 1: i2c_iir-ach
Info: Found entity 1: i2c_iir
Info: Found 2 design units, including 1 entities, in source file i2c_fir.vhd
Info: Found design unit 1: i2c_fir-ach
Info: Found entity 1: i2c_fir
Warning: Can't analyze file -- file E:/emtl/vgactr/i2c_up.vhd is missing
Warning: Can't analyze file -- file E:/emtl/vgactr/i2c_lw.vhd is missing
Info: Elaborating entity "pd" for the top level hierarchy
Info: Elaborating entity "vgactr" for hierarchy "vgactr:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf
Info: Found entity 1: lpm_mult
Info: Elaborating entity "lpm_mult" for hierarchy "vgactr:inst|lpm_mult:I_square"
Info: Found 1 design units, including 1 entities, in source file db/mult_ptr.tdf
Info: Found entity 1: mult_ptr
Info: Elaborating entity "mult_ptr" for hierarchy "vgactr:inst|lpm_mult:I_square|mult_ptr:auto_generated"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Elaborating entity "lpm_add_sub" for hierarchy "vgactr:inst|lpm_add_sub:square_sum"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_5pe.tdf
Info: Found entity 1: add_sub_5pe
Info: Elaborating entity "add_sub_5pe" for hierarchy "vgactr:inst|lpm_add_sub:square_sum|add_sub_5pe:auto_generated"
Info: Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 254 WYSIWYG logic cells and I/Os untouched
Info: Implemented 346 device resources after synthesis - the final resource count might be different
Info: Implemented 29 input pins
Info: Implemented 4 output pins
Info: Implemented 309 logic cells
Info: Implemented 4 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Processing ended: Sat Feb 02 11:39:20 2008
Info: Elapsed time: 00:00:06
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