fpga_dsp_portlink.sim.rpt

implemention of FPGA and DSP linking port, using Asynchronous mode

; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[7]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[7]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[7]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[7]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[6]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[6]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~74                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~74                                        ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[3]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[3]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[1]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[1]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[1]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[1]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[3]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[3]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~76                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~76                                        ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[5]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[5]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[5]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[5]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[2]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[2]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[3]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[3]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[4]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[4]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[5]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[5]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[6]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[6]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[7]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[7]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[8]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[8]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[9]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[9]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10]     ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10]     ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[2]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[2]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[3]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[3]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[4]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[4]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[5]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[5]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[6]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[6]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[7]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[7]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[8]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[8]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[9]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[9]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[10]                                                       ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrptr_g[10]                                                       ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[2]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[2]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[4]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[4]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera2                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera2~COUT                        ; cout             ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera3                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera3                             ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera3                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera3~COUT                        ; cout             ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera4                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera4                             ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera4                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera4~COUT                        ; cout             ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[8]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[8]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[10]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[10]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera5                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera5                             ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera5                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera5~COUT                        ; cout             ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera6                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera6                             ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera6                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera6~COUT                        ; cout             ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera7                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera7                             ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera7                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera7~COUT                        ; cout             ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera8                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera8                             ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera8                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera8~COUT                        ; cout             ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera9                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera9                             ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera9                             ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera9~COUT                        ; cout             ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera10                            ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera10                            ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[9]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[9]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[0]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[0]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[6]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe9a[6]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dc