⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 fpga_dsp_portlink.sim.rpt

📁 implemention of FPGA and DSP linking port, using Asynchronous mode
💻 RPT
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~516                                                                                                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~516                                                                                                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[8]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[8]        ; portadataout0    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[8]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[14]       ; portadataout1    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~517                                                                                                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~517                                                                                                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[6]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[6]        ; portadataout0    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~519                                                                                                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~519                                                                                                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[5]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[12]       ; portadataout1    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[4]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[4]        ; portadataout0    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[4]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[10]       ; portadataout1    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~521                                                                                                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~521                                                                                                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[3]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[3]        ; portadataout0    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[3]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[9]        ; portadataout1    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~522                                                                                                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~522                                                                                                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[2]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[2]        ; portadataout0    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[2]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[13]       ; portadataout1    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~523                                                                                                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~523                                                                                                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[2]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[2]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[4]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[4]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[4]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[4]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[2]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[2]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~77                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~77                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[8]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[8]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[10]       ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[10]       ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[10]     ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[10]     ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[8]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[8]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~78                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~78                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[9]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[9]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[0]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[0]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[6]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[6]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[7]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[7]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[7]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[7]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[6]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[6]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~80                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~80                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[3]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[3]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[1]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[1]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[3]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[3]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~82                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~82                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[5]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[5]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[5]      ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[5]      ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0                                          ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0                                          ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~525                                                                                                                         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~525                                                                                                                         ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[0]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[1]        ; portadataout1    ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[2]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[2]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[4]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[4]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[4]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[4]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[2]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[2]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~71                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~71                                        ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[8]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[8]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[10]                                                       ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[10]                                                       ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10]        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10]        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[8]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[8]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~72                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~72                                        ; combout          ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[9]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[9]                                                        ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[9]         ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[9]         ; regout           ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[6]                                                        ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[6]                                                        ; regout           ;
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -